CTNF 19/235,647 CTNF 96224 DETAILED ACTION The instant application having Application No. 19/235,647 has claims 38-67 pending in the application, all of which are ready for examination by the examiner. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application 19/235,647 filed 6/12/2025 is a Continuation of 17/405,946 filed 8/18/2021, now U.S. Patent #12353740. Claim Objections 07-29-01 AIA Claim s 38-50 are objected to because of the following informalities: For claim 38, the examiner recommends amending “wherein the plurality of memory partitions includes an authenticated-access partition…” as “wherein the plurality of memory partitions [[includes]] include an authenticated-access partition…” Claims 39-50 are objected for being dependent on an objected claim . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 47 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For claim 47, there is insufficient antecedent basis for the term ‘the global purge command’. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 08-34 AIA Claim s 38-47, 50-58, 60-66 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 6, and 8 of U.S. Patent No. 12353740 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the co-pending applications disclose/obviate the claims on the instant application . Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995. Instant application 19/235,647 U.S. Patent #12353740 (corresponding to Application #17/405,946) 38. (New) A flash memory, comprising: a plurality of memory partitions, wherein the plurality of memory partitions includes an authenticated-access partition and one or more non-authenticated-access partitions; a host interface; and a controller coupled to the host interface and the plurality of memory partitions and configured to: receive a local purge command through the host interface; and purge one or more de-mapped blocks only in the authenticated-access partition in response to the local purge command. 39. (New) The flash memory of claim 38, wherein the authenticated-access partition is a Replay- Protected Memory Block (RPMB). 40. (New) The flash memory of claim 38, wherein the authenticated-access partition comprises a plurality of regions. 41. (New) The flash memory of claim 40, wherein the authenticated-access partition consists of four regions. 42. (New) The flash memory of claim 40, wherein each region comprises a plurality of memory blocks. 43. (New) The flash memory of claim 40, wherein the controller is configured to purge only the one or more de-mapped blocks in a region of the plurality of regions in response to the local purge command. 44. (New) The flash memory of claim 43, wherein the region of the plurality of regions is indicated by the local purge command. 45. (New) The flash memory of claim 38, wherein the local purge command comprises an argument specifying a region within the authenticated-access partition. 46. (New) The flash memory of claim 38, wherein the controller is further configured to receive a global purge command; and purge one or more de-mapped blocks in the one or more non- authenticated-access partitions in response to the global purge command. 47. (New) The flash memory of claim 38, wherein controller is configured to purge all de- mapped blocks in the plurality of memory partitions in response to the global purge command. 6. A system for purging data from a memory device, comprising: a data storage medium, wherein the data storage medium comprises a plurality of storage partitions and each of the plurality of storage partitions comprises a plurality of physical memory blocks; and a controller coupled to the data storage medium, the controller configured to: de-map logical memory blocks from physical memory blocks of the plurality of storage partitions of the data storage medium; list de-mapped physical memory blocks only within a first storage partition of the plurality of storage partitions in a local de-mapped block list that is only associated with the first storage partition, the first storage partition is a Replay Protected Memory Block; list all de-mapped physical memory blocks of an entirety of the plurality of storage partitions of the data storage medium in a global de-mapped block list; receive a global purge command from a host device; purge the de-mapped physical memory blocks listed in the global de-mapped block list in response to the global purge command; generate a local purge command by the host device in order to purge only the de-mapped physical memory blocks within the first storage partition that are listed in the local de-mapped block list which is only associated with the first storage partition; receive the local purge command from the host device; purge only the de-mapped physical memory blocks listed in the local de-mapped block list which is only associated with the first storage partition in response to the local purge command; and list purged physical memory blocks of the first storage partition in a local free block list, wherein the local free block list is only associated with the first storage partition. 50. (New) The flash memory of claim 49, wherein the one or more de-mapped blocks in the authenticated-access partition contains key information associated with encrypted data stored in the one or more non-authenticated-access partitions. 8. The system of claim 6, wherein the controller is further configured to: form a plurality of units of encrypted data using a corresponding plurality of keys; store key information associated with the plurality of keys in the first storage partition; and store the plurality of units of encrypted data in a second storage partition of the plurality of storage partitions; wherein the controller is configured to de-map logical memory blocks from physical memory blocks of the first storage partition by being configured to de-map logical memory blocks associated with the plurality of keys from physical memory blocks storing the key information; wherein the controller is configured to purge the de-mapped physical memory blocks listed in the local de-mapped block list by being configured to purge physical memory blocks storing the key information. 51. (New) A system, comprising: a host system; and a flash memory coupled to the host system, wherein the flash memory includes an authenticated-access partition and one or more non-authenticated-access partition, and wherein the flash memory further includes a controller configured to receive a local purge command from the host system; and purge one or more de-mapped blocks only in the authenticated-access partition in response to the local purge command. 52. (New) The system of claim 51, wherein the authenticated-access partition is a Replay- Protected Memory Block (RPMB). 53. (New) The system of claim 51, wherein the authenticated-access partition comprises a plurality of regions. 54. (New) The flash memory of claim 53, wherein each region comprises a plurality of memory blocks. 55. (New) The flash memory of claim 53, wherein the controller is configured to purge the one or more de-mapped blocks only in a region of the plurality of regions in response to the local purge command. 56. (New) The flash memory of claim 55, wherein the region of the plurality of regions is indicated by the local purge command. 57. (New) The flash memory of claim 51, wherein the local purge command comprises an argument specifying a region within the authenticated-access partition. 58. (New) The flash memory of claim 51, wherein the controller is further configured to receive a global purge command; and purge one or more de-mapped blocks in the one or more non- authenticated-access partitions in response to the global purge command. 6. A system for purging data from a memory device, comprising: a data storage medium, wherein the data storage medium comprises a plurality of storage partitions and each of the plurality of storage partitions comprises a plurality of physical memory blocks; and a controller coupled to the data storage medium, the controller configured to: de-map logical memory blocks from physical memory blocks of the plurality of storage partitions of the data storage medium; list de-mapped physical memory blocks only within a first storage partition of the plurality of storage partitions in a local de-mapped block list that is only associated with the first storage partition, the first storage partition is a Replay Protected Memory Block; list all de-mapped physical memory blocks of an entirety of the plurality of storage partitions of the data storage medium in a global de-mapped block list; receive a global purge command from a host device; purge the de-mapped physical memory blocks listed in the global de-mapped block list in response to the global purge command; generate a local purge command by the host device in order to purge only the de-mapped physical memory blocks within the first storage partition that are listed in the local de-mapped block list which is only associated with the first storage partition; receive the local purge command from the host device; purge only the de-mapped physical memory blocks listed in the local de-mapped block list which is only associated with the first storage partition in response to the local purge command; and list purged physical memory blocks of the first storage partition in a local free block list, wherein the local free block list is only associated with the first storage partition. 60. (New) The flash memory of claim 51, wherein the one or more de-mapped blocks in the authenticated-access partition contains key information associated with encrypted data stored in the one or more non-authenticated-access partitions. 8. The system of claim 6, wherein the controller is further configured to: form a plurality of units of encrypted data using a corresponding plurality of keys; store key information associated with the plurality of keys in the first storage partition; and store the plurality of units of encrypted data in a second storage partition of the plurality of storage partitions; wherein the controller is configured to de-map logical memory blocks from physical memory blocks of the first storage partition by being configured to de-map logical memory blocks associated with the plurality of keys from physical memory blocks storing the key information; wherein the controller is configured to purge the de-mapped physical memory blocks listed in the local de-mapped block list by being configured to purge physical memory blocks storing the key information. 61. (New) A method by a flash memory system, comprising: receiving a local purge command from a host system; and purging one or more de-mapped blocks only in an authenticated-access partition in response to the local purge command, wherein the flash memory system includes the authenticated-access partition and one or more non-authenticated-access partition. 62. (New) The method of claim 61, wherein the authenticated-access partition is a Replay- Protected Memory Block (RPMB). 63. (New) The method of claim 61, wherein the authenticated-access partition comprises a plurality of regions, wherein each region of the plurality of regions comprises a plurality of memory blocks, and wherein the flash memory system is configured to purge the one or more de-mapped blocks only in a region of the plurality of regions in response to the local purge command. 64. (New) The method of claim 63, wherein the region of the plurality of regions is indicated by the local purge command. 65. (New) The method of claim 61, wherein the local purge command comprises an argument specifying a region within the authenticated-access partition. 66. (New) The method of claim 61, further comprising receiving a global purge command; and purging one or more de-mapped blocks in the one or more non-authenticated-access partitions in response to the global purge command. 1. A method for purging data from a memory device, comprising: de-mapping logical memory blocks from physical memory blocks of a plurality of storage partitions of the memory device, wherein each of the plurality of storage partitions comprises a plurality of physical memory blocks; listing de-mapped physical memory blocks only within a first storage partition of the plurality of storage partitions in a local de-mapped block list that is only associated with the first storage partition, the first storage partition is a Replay Protected Memory Block; listing all de-mapped physical memory blocks of an entirety of the plurality of storage partitions of the memory device in a global de-mapped block list; receiving a global purge command from a host device; purging the de-mapped physical memory blocks listed in the global de-mapped block list in response to the global purge command; generating a local purge command by the host device in order to purge only the de-mapped physical memory blocks within the first storage partition that are listed in the local de-mapped block list which is only associated with the first storage partition; receiving the local purge command from the host device; purging only the de-mapped physical memory blocks listed in the local de-mapped block list which is only associated with the first storage partition in response to the local purge command; and listing purged physical memory blocks of the first storage partition in a local free block list, wherein the local free block list is only associated with the first storage partition. U.S. Patent #12353740 discloses all limitations of the claims listed above except for flash memory, regions of an authenticated-access partition, and local purge command specifying a region within the authenticated-access partition. However, Jadon et al. (US 20250053338 A1) teaches a system comprising a system comprising flash memory having zones (partitions) comprising dies (regions) comprising erasable units (blocks) (para. 49-50, 83, 87 figs. 1A, 3A-B and associated paragraphs), where a trim request may explicitly specify trimming of a particular die and a purge request may similarly explicitly specify purging of invalid data in a die (para. 61-62, 64, 51, 4). U.S. Patent #12353740 and Jadon are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #12353740 and Jadon, to modify the disclosures by U.S. Patent #12353740 to include disclosures by Jadon since both they both teach data storage, wherein Jadon is directed towards greater efficiency in storage drives (para. 2-7). Therefore, it would be applying a known technique (system comprising zones comprising dies, where a die may be specified to be trimmed in a trimming request and specified to be purged in a purging request) to a known device (system providing for a local purge command for purging de-mapped blocks in a RPMB partition) ready for improvement to yield predictable results (system providing for a local purge command for purging de-mapped blocks in a RPMB partition, where the purge command may specify dies within a partition for de-mapping as well as for purging in order to provide for smaller command size and more efficient command transmission). MPEP 2143 The double patenting rejection above applies to claims 38-47, 50-58, and 60-66 . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 38-45, 51-57, and 61-65 are rejected under 35 U.S.C. 103 as being unpatentable over Jadon et al. (US 20250053338 A1) in view of Blodgett et al. (US 20190013081 A1) . As per claim 38, 38. (New) A flash memory, comprising: a plurality of memory partitions, wherein the plurality of memory partitions includes an authenticated-access partition and one or more non-authenticated-access partitions; a host interface; and a controller coupled to the host interface and the plurality of memory partitions and configured to: [Jadon teaches a storage system with flash memory that may receive commands from a host through an interface of a memory controller, the storage system comprising zones (partitions) having dies (regions) having erasure units (blocks) (para. 83, 87; figs. 3A-3B and associated paragraphs)] receive a local purge command through the host interface; and purge one or more de-mapped blocks only in the authenticated-access partition in response to the local purge command. [Jadon teaches the host may issue requests that specify, for example, a zone or a die to be trimmed and may also issue requests specifying a zone or die for purging any invalid data therein (local purge request) (para. 61-62, 64, 51, 4; fig. 1A and associated paragraphs), where it would have been obvious for one of ordinary arts to provide for, in association with a request for trimming a specific die, a request for purging the specific die to provide for improved memory utilization.] Jadon does not explicitly disclose the system to comprise an authenticated-access partition (or zone), but Blodgett discloses: an authenticated-access partition ; only in the authenticated-access partition [Blodgett discloses memory device that may comprise access-restricted RPMB regions, where the RPMB region may store sensitive data such as DRM keys that store data to specific memory areas (para. 58-59)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 39, Jadon in view of Blodgett teaches claim 38 as shown above and further teaches: 39. (New) The flash memory of claim 38, wherein the authenticated-access partition is a Replay-Protected Memory Block (RPMB). [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 40, Jadon in view of Blodgett teaches claim 38 as shown above and further teaches: 40. (New) The flash memory of claim 38, wherein the authenticated-access partition comprises a plurality of regions. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 41, Jadon in view of Blodgett teaches claim 40 as shown above and further teaches: 41. (New) The flash memory of claim 40, wherein the authenticated-access partition consists of four regions. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59); it would have been obvious for one of ordinary skill in the arts, before the effective filing date of the claimed invention, to have modified the number of dies associated with a zone as recited in the instant claim in order to optimize the balancing of address space size to be assigned to a zone based on usage requirements. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please also see MPEP 2144.05 II. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 809, 10 USPQ2d 1843, 1848 (Fed. Cir. 1989), cert. denied, 493 U.S. 975 (1989) (Claimed ratios were obvious as being reached by routine procedures and producing predictable results)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 42, Jadon in view of Blodgett teaches claim 40 as shown above and further teaches: 42. (New) The flash memory of claim 40, wherein each region comprises a plurality of memory blocks. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 43, Jadon in view of Blodgett teaches claim 40 as shown above and further teaches: 43. (New) The flash memory of claim 40, wherein the controller is configured to purge only the one or more de-mapped blocks in a region of the plurality of regions in response to the local purge command. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59), where a trim request may specify a die to be trimmed and a purge request may specify the die for purging invalid data (Jadon: para. 61-62, 64, 51, 4)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 44, Jadon in view of Blodgett teaches claim 43 as shown above and further teaches: 44. (New) The flash memory of claim 43, wherein the region of the plurality of regions is indicated by the local purge command. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59), where a trim request may specify a die to be trimmed and a purge request may specify the die for purging invalid data (Jadon: para. 61-62, 64, 51, 4)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 45, Jadon in view of Blodgett teaches claim 38 as shown above and further teaches: 45. (New) The flash memory of claim 38, wherein the local purge command comprises an argument specifying a region within the authenticated-access partition. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59), where a trim request may specify a die to be trimmed and a purge request may specify the die for purging invalid data (Jadon: para. 61-62, 64, 51, 4; see para. 64 indicating an express field of the request specifying a structure)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 51, 51. (New) A system, comprising: a host system; and a flash memory coupled to the host system, wherein the flash memory includes an authenticated-access partition and one or more non-authenticated-access partition, and wherein the flash memory further includes a controller configured to [Jadon teaches a storage system with flash memory that may receive commands from a host through an interface of a memory controller, the storage system comprising zones (partitions) having dies (regions) having erasure units (blocks) (para. 83, 87; figs. 3A-3B and associated paragraphs)] receive a local purge command from the host system; and purge one or more de-mapped blocks only in the authenticated-access partition in response to the local purge command. [Jadon teaches the host may issue requests that specify, for example, a zone or a die to be trimmed and may also issue requests specifying a zone or die for purging any invalid data therein (local purge request) (para. 61-62, 64, 51, 4; fig. 1A and associated paragraphs), where it would have been obvious for one of ordinary arts to provide for, in association with a request for trimming a specific die, a request for purging the specific die to provide for improved memory utilization.] Jadon does not explicitly disclose the system to comprise an authenticated-access partition (or zone), but Blodgett discloses: authenticated-access partition ; only in the authenticated-access partition [Blodgett discloses memory device that may comprise access-restricted RPMB regions, where the RPMB region may store sensitive data such as DRM keys that store data to specific memory areas (para. 58-59)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). Claim 52 is rejected for reasons similar to claim 39. Claim 53 is rejected for reasons similar to claim 40. Claim 54 is rejected for reasons similar to claim 42. As per claim 55, Jadon in view of Blodgett teaches claim 53 as shown above and further teaches: 55. (New) The flash memory of claim 53, wherein the controller is configured to purge the one or more de-mapped blocks only in a region of the plurality of regions in response to the local purge command. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 51 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59), where a trim request may specify a die to be trimmed and a purge request may specify the die for purging invalid data (Jadon: para. 61-62, 64, 51, 4)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 56, Jadon in view of Blodgett teaches claim 55 as shown above and further teaches: 56. (New) The flash memory of claim 55, wherein the region of the plurality of regions is indicated by the local purge command. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 51 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59), where a trim request may specify a die to be trimmed and a purge request may specify the die for purging invalid data (Jadon: para. 61-62, 64, 51, 4)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). Claim 57 is rejected for reasons similar to claim 45. As per claim 61, 61. (New) A method by a flash memory system, comprising: [Jadon teaches a storage system with flash memory that may receive commands from a host through an interface of a memory controller, the storage system comprising zones (partitions) having dies (regions) having erasure units (blocks) (para. 83, 87; figs. 3A-3B and associated paragraphs)] receiving a local purge command from a host system; and purging one or more de-mapped blocks only in an authenticated-access partition in response to the local purge command, wherein the flash memory system includes the authenticated-access partition and one or more non-authenticated-access partition. [Jadon teaches the host may issue requests that specify, for example, a zone or a die to be trimmed and may also issue requests specifying a zone or die for purging any invalid data therein (local purge request) (para. 61-62, 64, 51, 4; fig. 1A and associated paragraphs), where it would have been obvious for one of ordinary arts to provide for, in association with a request for trimming a specific die, a request for purging the specific die to provide for improved memory utilization.] Jadon does not explicitly disclose the system to comprise an authenticated-access partition (or zone), but Blodgett discloses: only in an authenticated-access partition ; the authenticated-access partition [Blodgett discloses memory device that may comprise access-restricted RPMB regions, where the RPMB region may store sensitive data such as DRM keys that store data to specific memory areas (para. 58-59)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). Claim 62 is rejected for reasons similar to claim 39. As per claim 63, Jadon in view of Blodgett teaches claim 61 as shown above and further teaches: 63. (New) The method of claim 61, wherein the authenticated-access partition comprises a plurality of regions, wherein each region of the plurality of regions comprises a plurality of memory blocks, and wherein the flash memory system is configured to purge the one or more de-mapped blocks only in a region of the plurality of regions in response to the local purge command. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59), where a trim request may specify a die to be trimmed and a purge request may specify the die for purging invalid data (Jadon: para. 61-62, 64, 51, 4)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). As per claim 64, Jadon in view of Blodgett teaches claim 63 as shown above and further teaches: 64. (New) The method of claim 63, wherein the region of the plurality of regions is indicated by the local purge command. [Jadon in view of Blodgett as shown above teaches configuring a zone as RPMB, where a zone comprises a plurality of dies (regions) comprising erasure units (blocks) (see claim 38 above; Jadon: para. 61-62, 64, 51, 4, 83, 87; Blodgett: para. 58-59), where a trim request may specify a die to be trimmed and a purge request may specify the die for purging invalid data (Jadon: para. 61-62, 64, 51, 4)] Jadon and Blodgett are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the disclosures provided by Jadon with Blodgett’s disclosures directed towards configuring a region of a memory device as an RPMB region to provide for a combination comprising configuring at least a zone among a plurality of zones as RPMB. Doing so would allow for improved data security by providing for storage of sensitive information in a protected manner (para. 59). Claim 65 is rejected for reasons similar to claim 45 . 07-21-aia AIA Claim s 46-48, 58-59, and 66-67 are rejected under 35 U.S.C. 103 as being unpatentable over Jadon et al. (US 20250053338 A1) in view of Blodgett et al. (US 20190013081 A1) in view of Tagawa et al. (US 20080235467 A1) . As per claim 46, Jadon in view of Blodgett teaches claim 38 as shown above. It does not explicitly disclose, but Tagawa teaches: 46. (New) The flash memory of claim 38, wherein the controller is further configured to receive a global purge command; and purge one or more de-mapped blocks in the one or more non- authenticated-access partitions in response to the global purge command. [Tagawa teaches an initialize command designed to be used without a parameter for initializing the whole area of a storage device (para. 85), the initializing including erasing all the blocks in the flash memories of the system (para. 92-95; figs. 1, 5-6 and associated paragraphs), where the command would necessarily erase (purge) blocks including invalid blocks of the system] Jadon, Blodgett, and Tagawa are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jadon in view of Blodgett and Tagawa, to modify the disclosures by Jadon in view of Blodgett to include disclosures by Tagawa since they both teach data storage, wherein Tagawa is directed towards improved memory management methods (para. 14). Therefore, it would be applying a known technique (initialize command for erasing all blocks of a memory system) to a known device (system comprising a plurality of zones) ready for improvement to yield predictable results (system comprising a plurality of zones, where an initialize command be used for erasing all the blocks of the system; doing so would provide for a method for efficiently wiping a memory of potentially sensitive data). MPEP 2143 As per claim 47, Jadon in view of Blodgett teaches claim 38 as shown above. It does not explicitly disclose, but Tagawa discloses: 47. (New) The flash memory of claim 38, wherein controller is configured to purge all de- mapped blocks in the plurality of memory partitions in response to the global purge command. [Tagawa teaches an initialize command designed to be used without a parameter for initializing the whole area of a storage device (para. 85), the initializing including erasing all the blocks in the flash memories of the system (para. 92-95; figs. 1, 5-6 and associated paragraphs), where the command would necessarily erase (purge) blocks including invalid blocks of the system] Jadon, Blodgett, and Tagawa are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jadon in view of Blodgett and Tagawa, to modify the disclosures by Jadon in view of Blodgett to include disclosures by Tagawa since they both teach data storage, wherein Tagawa is directed towards improved memory management methods (para. 14). Therefore, it would be applying a known technique (initialize command for erasing all blocks of a memory system) to a known device (system comprising a plurality of zones) ready for improvement to yield predictable results (system comprising a plurality of zones, where an initialize command be used for erasing all the blocks of the system; doing so would provide for a method for efficiently wiping a memory of potentially sensitive data). MPEP 2143 As per claim 48, Jadon in view of Blodgett in view of Tagawa teaches claim 47 as shown above and further teaches: 48. (New) The flash memory of claim 46, wherein the global purge command takes no arguments. [Jadon in view of Blodgett in view of Tagawa as shown above teaches an initialize command designed to be used without a parameter for initializing the whole area of a storage device (para. 85), the initializing including erasing all the blocks in the flash memories of the system (para. 92-95; figs. 1, 5-6 and associated paragraphs), where the command would necessarily erase (purge) blocks including invalid blocks of the system] Jadon, Blodgett, and Tagawa are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jadon in view of Blodgett and Tagawa, to modify the disclosures by Jadon in view of Blodgett to include disclosures by Tagawa since they both teach data storage, wherein Tagawa is directed towards improved memory management methods (para. 14). Therefore, it would be applying a known technique (initialize command for erasing all blocks of a memory system) to a known device (system comprising a plurality of zones) ready for improvement to yield predictable results (system comprising a plurality of zones, where an initialize command be used for erasing all the blocks of the system; doing so would provide for a method for efficiently wiping a memory of potentially sensitive data). MPEP 2143 Claim 58 is rejected for reasons similar to claim 46. Claim 59 is rejected for reasons similar to claim 48. Claim 66 is rejected for reasons similar to claim 46. Claim 67 is rejected for reasons similar to claim 48 . 07-21-aia AIA Claim 49 is rejected under 35 U.S.C. 103 as being unpatentable over Jadon et al. (US 20250053338 A1) in view of Blodgett et al. (US 20190013081 A1) in view of Tagawa et al. (US 20080235467 A1) in view of Harasawa et al. (US 20180039448 A1) . As per claim 49, Jadon in view of Blodgett in view of Tagawa teaches claim 46 as shown above. It does not explicitly discloses, but Harasawa teaches: 49. (New) The flash memory of claim 46, wherein the global purge command is a Format Unit command. [Harasawa teaches a format unit command used to initialize all regions of a memory device (para. 106)] Jadon, Blodgett, Tagawa, and Harasawa are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Jadon in view of Blodgett in view of Tagawa and Harasawa, to modify the teachings of Jadon in view of Blodgett in view of Tagawa to include the teaching of Harasawa since they both teach data storage, wherein Harasawa is directed towards improved reliability in storage (para. 3). Therefore, it would have been a simple substitution of one type of command (format unit command) for another command ready for improvement to provide predictable results (utilizing a command stipulated in a SCSI standard to provide for greater modularity with different memory devices used with a host). MPEP 2143 07-21-aia AIA Claim 50 is rejected under 35 U.S.C. 103 as being unpatentable over Jadon et al. (US 20250053338 A1) in view of Blodgett et al. (US 20190013081 A1) in view of Tagawa et al. (US 20080235467 A1) in view of Harasawa et al. (US 20180039448 A1) in view of in view of Ostrovsky et al. (US 20220012172 A1) . As per claim 50, Jadon in view of Blodgett in view of Tagawa in view of Harasawa teaches claim 49 as shown above. It does not explicitly discloses, but Ostrovsky teaches: 50. (New) The flash memory of claim 49, wherein the one or more de-mapped blocks in the authenticated-access partition contains key information associated with encrypted data stored in the one or more non-authenticated-access partitions. [Jadon in view of Blodgett in view of Tagawa in view of Harasawa as shown above provides for a RPMB zone comprising sensitive data such as DRM keys that store data to specific memory areas (see claim 38 above; Blodgett: para. 58-59) and trimming/purging of zones/dies (Jadon: para. 61-62, 64, 51, 4); while Jadon in view of Blodgett in view of Tagawa in view of Harasawa does not specifically recite DRM keys being associated with encrypted data in other zones, Ostrovsky teaches encrypting data with keys and storing the encrypted data (para. 217-218; fig. 5 and associated paragraphs), where the keys may be stored separately from the encrypted data in different blocks/region (para. 220)] Jadon, Blodgett, Tagawa, Harasawa, and Ostrovsky are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jadon in view of Blodgett in view of Tagawa in view of Harasawa and Ostrovsky, to modify the disclosures by Jadon in view of Blodgett in view of Tagawa in view of Harasawa to include disclosures by Ostrovsky since they both teach data storage, wherein Ostrovsky is directed towards improved data security (para. 208). Therefore, it would be applying a known technique (using keys to encrypt data and storing keys separately from encrypted data) to a known device (system comprising an RPMB zone for storing sensitive data including DRM keys storing data to specific memory areas) ready for improvement to yield predictable results (system comprising an RPMB zone for storing sensitive data including keys used to encrypt data stored separately in other zones in order to provide for improved security over encryption information associated with stored data). MPEP 2143 07-21-aia AIA Claim 60 is rejected under 35 U.S.C. 103 as being unpatentable over Jadon et al. (US 20250053338 A1) in view of Blodgett et al. (US 20190013081 A1) in view of in view of Ostrovsky et al. (US 20220012172 A1) . As per claim 60, Jadon in view of Blodgett teaches claim 51 as shown above. It does note explicitly disclose, but Ostrovsky teaches: 60. (New) The flash memory of claim 51, wherein the one or more de-mapped blocks in the authenticated-access partition contains key information associated with encrypted data stored in the one or more non-authenticated-access partitions. [Jadon in view of Blodgett as shown above provides for a RPMB zone comprising sensitive data such as DRM keys that store data to specific memory areas (see claim 51 above; Blodgett: para. 58-59) and trimming/purging of zones/dies (Jadon: para. 61-62, 64, 51, 4); while Jadon in view of Blodgett does not specifically recite DRM keys being associated with encrypted data in other zones, Ostrovsky teaches encrypting data with keys and storing the encrypted data (para. 217-218; fig. 5 and associated paragraphs), where the keys may be stored separately from the encrypted data in different blocks/region (para. 220)] Jadon, Blodgett, and Ostrovsky are analogous to the claimed invention because they are in the same field of endeavor involving data storage. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of Jadon in view of Blodgett and Ostrovsky, to modify the disclosures by Jadon in view of Blodgett to include disclosures by Ostrovsky since they both teach data storage, wherein Ostrovsky is directed towards improved data security (para. 208). Therefore, it would be applying a known technique (using keys to encrypt data and storing keys separately from encrypted data) to a known device (system comprising an RPMB zone for storing sensitive data including DRM keys storing data to specific memory areas) ready for improvement to yield predictable results (system comprising an RPMB zone for storing sensitive data including keys used to encrypt data stored separately in other zones in order to provide for improved security over encryption information associated with stored data). MPEP 2143 Relevant Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Park et al. (US 20180032541 A1) teaches an erase command that may erase all invalid data in a storage system . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS KIM whose telephone number is (571)272-8093. The examiner can normally be reached Monday - Friday: 7:30-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JARED RUTZ can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.Y.K./Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135 Application/Control Number: 19/235,647 Page 2 Art Unit: 2135 Application/Control Number: 19/235,647 Page 3 Art Unit: 2135 Application/Control Number: 19/235,647 Page 4 Art Unit: 2135 Application/Control Number: 19/235,647 Page 5 Art Unit: 2135 Application/Control Number: 19/235,647 Page 6 Art Unit: 2135 Application/Control Number: 19/235,647 Page 7 Art Unit: 2135 Application/Control Number: 19/235,647 Page 8 Art Unit: 2135 Application/Control Number: 19/235,647 Page 9 Art Unit: 2135 Application/Control Number: 19/235,647 Page 10 Art Unit: 2135 Application/Control Number: 19/235,647 Page 11 Art Unit: 2135 Application/Control Number: 19/235,647 Page 12 Art Unit: 2135 Application/Control Number: 19/235,647 Page 13 Art Unit: 2135 Application/Control Number: 19/235,647 Page 14 Art Unit: 2135 Application/Control Number: 19/235,647 Page 15 Art Unit: 2135 Application/Control Number: 19/235,647 Page 16 Art Unit: 2135 Application/Control Number: 19/235,647 Page 17 Art Unit: 2135 Application/Control Number: 19/235,647 Page 18 Art Unit: 2135 Application/Control Number: 19/235,647 Page 19 Art Unit: 2135 Application/Control Number: 19/235,647 Page 20 Art Unit: 2135 Application/Control Number: 19/235,647 Page 21 Art Unit: 2135 Application/Control Number: 19/235,647 Page 22 Art Unit: 2135 Application/Control Number: 19/235,647 Page 23 Art Unit: 2135 Application/Control Number: 19/235,647 Page 24 Art Unit: 2135 Application/Control Number: 19/235,647 Page 25 Art Unit: 2135 Application/Control Number: 19/235,647 Page 26 Art Unit: 2135 Application/Control Number: 19/235,647 Page 27 Art Unit: 2135 Application/Control Number: 19/235,647 Page 28 Art Unit: 2135 Application/Control Number: 19/235,647 Page 29 Art Unit: 2135 Application/Control Number: 19/235,647 Page 30 Art Unit: 2135 Application/Control Number: 19/235,647 Page 31 Art Unit: 2135 Application/Control Number: 19/235,647 Page 32 Art Unit: 2135 Application/Control Number: 19/235,647 Page 33 Art Unit: 2135 Application/Control Number: 19/235,647 Page 34 Art Unit: 2135 Application/Control Number: 19/235,647 Page 35 Art Unit: 2135 Application/Control Number: 19/235,647 Page 36 Art Unit: 2135 Application/Control Number: 19/235,647 Page 37 Art Unit: 2135 Application/Control Number: 19/235,647 Page 38 Art Unit: 2135
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