DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/12/2025 and 09/08/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4, 17 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “BAN algorithm” in claims 3-4, 17 and 20 is a relative term which renders the claim indefinite. The term “BAN algorithm” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
For the purpose of examination, the term “BAN algorithm” is being interpreted as a block level mapping algorithm.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because:
As per claims 18-20, they are rejected because the applicant has provided evidence that the applicant intends the term "computer-readable storage medium” to include non-statutory matter. The applicant describes a computer-readable storage medium as including open ended language and thus it is reasonable to interpret it to include all possible mediums, including non-statutory mediums (see paragraph 288). The words "storage" and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claim(s) is/are drawn to a form of energy. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter.
The Examiner suggests amending the claim(s) to read as a “non-transitory computer-readable storage medium”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11, 15 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Palmer (US2022/0107886).
With respect claim 1, Palmer teaches a flash translation layer algorithm, applied to a solid state drive, wherein a plurality of FTL algorithms are stored in the solid state drive (see Fig. 1 and paragraphs 25 and 34; Two or more FTLs 180 may be included as part of a memory device 130 or memory system 110), and the plurality of FTL algorithms comprise a first FTL algorithm and a second FTL algorithm (see Fig. 1 and paragraph 34; two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity and a second FTL 180 (e.g., a secondary or smaller FTL 180) may be configured to support data mapping using a smaller granularity than the defined granularity); and the method comprises:
determining address mapping information based on the first FTL algorithm during a time period (see Fig. 1 and paragraphs 25 and 34; Two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity), wherein the address mapping information indicates a correspondence between a logical address and a physical address of the solid state drive during processing a read/write task (see paragraphs 53-57 and 69-70; the memory device receives a write command from the host system or the host device (e.g., or other source external to the memory device) to write data, the memory device (e.g., a controller of the memory device) may select between using the FTL and the other FTL for storing and mapping the data (e.g., as described with reference to FIGS. 2 and 3). If the FTL is selected, the memory device may identify a logical address associated with the data (e.g., as specified in the write command) and may identify the range 405 associated with the logical address and whether any nodes 415 have been defined for the range 405… When building or creating information for a node 415, the memory device may include an indication of a logical address, a physical address, a left pointer 420, and a right pointer 420 for the associated node. The logical and physical addresses may respectively represent the logical and physical addresses of the data associated with the node 415 (e.g., for L2P mapping));
determining a second FTL algorithm from the plurality of FTL algorithms (see Fig. 1 and paragraph 34; two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity and a second FTL 180 (e.g., a secondary or smaller FTL 180) may be configured to support data mapping using a smaller granularity than the defined granularity); wherein performance of processing the read/write task during the time period based on the second FTL algorithm is higher than performance of processing the read/write task during the time period based on the first FTL algorithm (see paragraph 45; FTL 220-b may be configured to map data that may be smaller than the defined granularity, data that may be aligned such that a portion of the data is smaller than the defined granularity... Doing so may decrease latency, decrease write amplification and wear, and increase device lifetime and performance); and
controlling the solid state drive to enable target address mapping information determined based on the second FTL algorithm (see Fig. 3 and paragraphs 50-63; If the memory device 205 receives, for example, a read command to read data, FTL 220-b may identify (e.g., from the read command) one or more logical addresses associated with the data. FTL 220-b may look up the one or more logical addresses using the data mapping (e.g., L2P table) and, if the data is associated with FTL 220-b, FTL 220-b may return one or more physical addresses corresponding to the one or more logical addresses).
With respect claim 11, Palmer teaches wherein the determining of the second FTL algorithm from the plurality of FTL algorithms comprises: based on a received target instruction, determining the second FTL algorithm from the plurality of FTL algorithms, wherein the target instruction indicates the second FTL algorithm (see paragraphs 53 and 72; data may be received (e.g., at a controller or an interface) for writing to the memory device. The data may be received within or in relation to a write command from a source external to the memory device, such as a host system or a host device. The memory device may identify one or more logical addresses for the data... The memory device may evaluate the data to determine one or more characteristics of the data and to determine whether the one or more characteristics of the data match the first FTL or the second FTL).
With respect claim 15, Palmer teaches computer device, comprising a processor connected to a memory (see Fig. 1 and paragraph 16; system 100 may include a host system 105, which may be coupled with the memory system 110… host system 105 may include one or more devices, and in some cases may include a processor chipset);
wherein the memory is configured to store a computer-executable instruction, and the processor executes the computer-executable instruction stored in the memory (see Fig. 1 and paragraph 22; local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controller 115 to perform functions) to enable the computer device to control a solid state drive to determine a flash translation layer algorithm, wherein a plurality of FTL algorithms are stored in the solid state drive (see Fig. 1 and paragraphs 25 and 34; Two or more FTLs 180 may be included as part of a memory device 130 or memory system 110), and the plurality of FTL algorithms comprise a first FTL algorithm and a second FTL algorithm (see Fig. 1 and paragraph 34; two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity and a second FTL 180 (e.g., a secondary or smaller FTL 180) may be configured to support data mapping using a smaller granularity than the defined granularity), and wherein the computer device is enabled to control the solid device to:
determine address mapping information based on the first FTL algorithm during a time period (see Fig. 1 and paragraphs 25 and 34; Two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity), wherein the address mapping information indicates a correspondence between a logical address and a physical address of the solid state drive when processing a read/write task (see paragraphs 53-57 and 69-70; the memory device receives a write command from the host system or the host device (e.g., or other source external to the memory device) to write data, the memory device (e.g., a controller of the memory device) may select between using the FTL and the other FTL for storing and mapping the data (e.g., as described with reference to FIGS. 2 and 3). If the FTL is selected, the memory device may identify a logical address associated with the data (e.g., as specified in the write command) and may identify the range 405 associated with the logical address and whether any nodes 415 have been defined for the range 405… When building or creating information for a node 415, the memory device may include an indication of a logical address, a physical address, a left pointer 420, and a right pointer 420 for the associated node. The logical and physical addresses may respectively represent the logical and physical addresses of the data associated with the node 415 (e.g., for L2P mapping));
determine a second FTL algorithm from the plurality of FTL algorithms (see Fig. 1 and paragraph 34; two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity and a second FTL 180 (e.g., a secondary or smaller FTL 180) may be configured to support data mapping using a smaller granularity than the defined granularity); wherein performance of processing the read/write task during the time period based on the second FTL algorithm is higher than performance of processing the read/write task during the time period based on the first FTL algorithm (see paragraph 45; FTL 220-b may be configured to map data that may be smaller than the defined granularity, data that may be aligned such that a portion of the data is smaller than the defined granularity... Doing so may decrease latency, decrease write amplification and wear, and increase device lifetime and performance); and
control the solid state drive to enable target address mapping information determined based on the second FTL algorithm (see Fig. 3 and paragraphs 50-63; If the memory device 205 receives, for example, a read command to read data, FTL 220-b may identify (e.g., from the read command) one or more logical addresses associated with the data. FTL 220-b may look up the one or more logical addresses using the data mapping (e.g., L2P table) and, if the data is associated with FTL 220-b, FTL 220-b may return one or more physical addresses corresponding to the one or more logical addresses).
With respect claim 18, Palmer teaches computer-readable storage medium for storing a computer instruction, wherein the computer instruction is executed on a computer (see Fig. 1 and paragraph 22; local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controller 115 to perform functions), enabling the computer to control a solid state drive to determine a flash translation layer algorithm, wherein a plurality of FTL algorithms are stored in the solid state drive (see Fig. 1 and paragraphs 25 and 34; Two or more FTLs 180 may be included as part of a memory device 130 or memory system 110), and the plurality of FTL algorithms comprise a first FTL algorithm and a second FTL algorithm (see Fig. 1 and paragraph 34; two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity and a second FTL 180 (e.g., a secondary or smaller FTL 180) may be configured to support data mapping using a smaller granularity than the defined granularity), and wherein the computer device is enabled to control the solid device to:
determine address mapping information based on the first FTL algorithm during a time period (see Fig. 1 and paragraphs 25 and 34; Two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity), wherein the address mapping information indicates a correspondence between a logical address and a physical address of the solid state drive when processing a read/write task (see paragraphs 53-57 and 69-70; the memory device receives a write command from the host system or the host device (e.g., or other source external to the memory device) to write data, the memory device (e.g., a controller of the memory device) may select between using the FTL and the other FTL for storing and mapping the data (e.g., as described with reference to FIGS. 2 and 3). If the FTL is selected, the memory device may identify a logical address associated with the data (e.g., as specified in the write command) and may identify the range 405 associated with the logical address and whether any nodes 415 have been defined for the range 405… When building or creating information for a node 415, the memory device may include an indication of a logical address, a physical address, a left pointer 420, and a right pointer 420 for the associated node. The logical and physical addresses may respectively represent the logical and physical addresses of the data associated with the node 415 (e.g., for L2P mapping));
determine a second FTL algorithm from the plurality of FTL algorithms (see Fig. 1 and paragraph 34; two or more FTLs 180 may be included as part of a memory device 130 or memory system 110, where a first FTL 180 (e.g., a primary FTL 180 using a larger granularity) may be configured to support data mapping using a defined granularity and a second FTL 180 (e.g., a secondary or smaller FTL 180) may be configured to support data mapping using a smaller granularity than the defined granularity); wherein performance of processing the read/write task during the time period based on the second FTL algorithm is higher than performance of processing the read/write task during the time period based on the first FTL algorithm (see paragraph 45; FTL 220-b may be configured to map data that may be smaller than the defined granularity, data that may be aligned such that a portion of the data is smaller than the defined granularity... Doing so may decrease latency, decrease write amplification and wear, and increase device lifetime and performance); and
control the solid state drive to enable target address mapping information determined based on the second FTL algorithm (see Fig. 3 and paragraphs 50-63; If the memory device 205 receives, for example, a read command to read data, FTL 220-b may identify (e.g., from the read command) one or more logical addresses associated with the data. FTL 220-b may look up the one or more logical addresses using the data mapping (e.g., L2P table) and, if the data is associated with FTL 220-b, FTL 220-b may return one or more physical addresses corresponding to the one or more logical addresses).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 5-8, 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US2022/0107886) in view of Kim et al. (US2006/0179212).
With respect claim 2, Palmer does not teach wherein the determining of the second FTL algorithm from the plurality of FTL algorithms comprises: according to a read/write condition of a plurality of read/write tasks processed based on the first FTL algorithm during the time period, determining a target read/write type; and based on the target read/write type, determining the second FTL algorithm from the plurality of FTL algorithms.
However, Kim et al. teaches wherein an access pattern can be figured out by extracting the logical address information from the incoming data received from the host processor. If the extracted logical address information is an address for storing the FAT data, the current access request is determined as a random single write request. Otherwise, if the extracted logical address information is not an address for storing the FAT data, the current access request is determined as a sequential write request (see paragraph 34)… and it is possible to accumulate information on whether there are frequent random single write requests or whether there are frequent sequential write requests for an arbitrary region, and select a flash translation layer based on the accumulated information. Also, it is possible to select a flash translation layer based on information provided from the outside (e.g., information on the pattern of the current access) (i.e., based on access patterns it is determined if request is single write request or sequential write request) (see paragraph 36).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer to include the above mentioned to prevent the performance of the entire system from degrading by using a flash translation layer suitable for each request (see Kim, paragraph 33).
With respect claim 5, Palmer does not teach wherein according to the read or write condition of the plurality of read or write tasks processed based on the first FTL algorithm during the time period, the determining of the target read/write type comprises: based on a proportion of read tasks among the plurality of read/write tasks or a proportion of a write task among the plurality of read/write tasks, determining the target read/write type.
However, Kim et al. teaches wherein it is possible to accumulate information on whether there are frequent random single write requests or whether there are frequent sequential write requests for an arbitrary region, and select a flash translation layer based on the accumulated information. Also, it is possible to select a flash translation layer based on information provided from the outside (e.g., information on the pattern of the current access) (i.e., based on a number/proportion of access patterns it is determined if request is single write request or sequential write request) (see paragraph 36).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer to include the above mentioned to prevent the performance of the entire system from degrading by using a flash translation layer suitable for each request (see Kim, paragraph 33).
With respect claim 6, Palmer does not teach wherein based on the proportion of the read task among the plurality of read/write tasks or the proportion of the write task among the plurality of read/write tasks, the determining of the target read/write type, comprises: based on the proportion of the read task among the plurality of read/write tasks and a fluctuation of the proportion of the read task during a target time period, or the proportion of the write task among the plurality of read/write tasks and a fluctuation of the proportion of the write task during a target time period, determining the target read/write type.
However, Kim et al. teaches wherein when an external access is requested, determining a pattern of the access, selecting one of the flash translation layers stored in the memory based on the determination result, and managing mapping data of the flash memory based on the selected flash translation layer (see paragraph 17)… it is possible to accumulate information on whether there are frequent random single write requests or whether there are frequent sequential write requests for an arbitrary region, and select a flash translation layer based on the accumulated information. Also, it is possible to select a flash translation layer based on information provided from the outside (e.g., information on the pattern of the current access) (see paragraph 36).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer to include the above mentioned to prevent the performance of the entire system from degrading by using a flash translation layer suitable for each request (see Kim, paragraph 33).
With respect claim 7, Palmer does not teach wherein based on the proportion of the read task among the plurality of read/write tasks and the fluctuation of the proportion of the read task during the target time period, the determining of the target read/write type comprises: in a case that the proportion of the read task among the plurality of read/write tasks is greater than or equal to a first threshold and a fluctuation ratio of the proportion of the read task during the target time period is less than or equal to a second threshold, determining the target read/write type as the read task; or, based on the proportion of the write task among the plurality of read/write tasks and the fluctuation of the proportion of the write task during the target time period, the determining of the target read/write type comprises: in a case that the proportion of the write task among the plurality of read/write tasks is greater than or equal to a third threshold and a fluctuation ratio of the proportion of the write task during the target time period is less than or equal to a fourth threshold, determining the target read/write type as the write task.
However, Kim et al. teaches wherein it is possible to accumulate information on whether there are frequent random single write requests or whether there are frequent sequential write requests for an arbitrary region, and select a flash translation layer based on the accumulated information. Also, it is possible to select a flash translation layer based on information provided from the outside (e.g., information on the pattern of the current access) (see paragraph 36).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer to include the above mentioned to prevent the performance of the entire system from degrading by using a flash translation layer suitable for each request (see Kim, paragraph 33).
With respect claim 8, Palmer does not teach wherein according to the read/write condition of the plurality of read/write tasks processed based on the first FTL algorithm during the time period, the determining of the target read/write type comprises: based on at least one of a proportion of a random read task among the plurality of read/write tasks, a proportion of a sequential read task among the plurality of read/write tasks, a proportion of a random write task among the plurality of read/write tasks, or a proportion of a sequential write task among the plurality of read/write tasks, determining the target read/write type.
However, Kim et al. teaches wherein it is possible to accumulate information on whether there are frequent random single write requests or whether there are frequent sequential write requests for an arbitrary region, and select a flash translation layer based on the accumulated information. Also, it is possible to select a flash translation layer based on information provided from the outside (e.g., information on the pattern of the current access) (i.e., based on a number/proportion of access patterns it is determined if request is single write request or sequential write request) (see paragraph 36).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer to include the above mentioned to prevent the performance of the entire system from degrading by using a flash translation layer suitable for each request (see Kim, paragraph 33).
With respect claim 16, Palmer does not teach wherein the determining of the second FTL algorithm from the plurality of FTL algorithms comprises: according to a read/write condition of a plurality of read/write tasks processed based on the first FTL algorithm during the time period, determining a target read/write type; and based on the target read/write type, determining the second FTL algorithm from the plurality of FTL algorithms.
However, Kim et al. teaches wherein an access pattern can be figured out by extracting the logical address information from the incoming data received from the host processor. If the extracted logical address information is an address for storing the FAT data, the current access request is determined as a random single write request. Otherwise, if the extracted logical address information is not an address for storing the FAT data, the current access request is determined as a sequential write request (see paragraph 34)… and it is possible to accumulate information on whether there are frequent random single write requests or whether there are frequent sequential write requests for an arbitrary region, and select a flash translation layer based on the accumulated information. Also, it is possible to select a flash translation layer based on information provided from the outside (e.g., information on the pattern of the current access) (i.e., based on access patterns it is determined if request is single write request or sequential write request) (see paragraph 36).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Palmer to include the above mentioned to prevent the performance of the entire system from degrading by using a flash translation layer suitable for each request (see Kim, paragraph 33).
With respect claim 19, Palmer does not teach wherein the determining of the second FTL algorithm from the plurality of FTL algorithms comprises: according to a read/write condition of a plurality of read/write tasks processed based on the first FTL algorithm during the time period, determining a target read/write type; and based on the target read/write type, determining the second FTL algorithm from the plurality of FTL algorithms.
However, Kim et al. teaches wherein an access pattern can be figured out by extracting the logical address information from the incoming data received from the host processor. If the extracted logical address information is an address for storing the FAT data, the current access request is determined as a random single write request. Otherwise, if the extracted logical address information is not an address for storing the FAT data, the current access request is determined as a sequential write request (see paragraph 34)… and it is possible to accumulate information on whether there are frequent random single write requests or whether there are frequent sequential write requests for an arbitrary region, and select a flash translation layer based on the accumulated information. Also, it is possible to select a flash translation layer based on information provided from the outside (e.g., information on the pattern of the current access) (i.e., based on access patterns it is determined if request is single write request or sequential write request) (see paragraph 36).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Palmer to include the above mentioned to prevent the performance of the entire system from degrading by using a flash translation layer suitable for each request (see Kim, paragraph 33).
Claim(s) 3-4, 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palmer (US2022/0107886) and Kim et al. (US2006/0179212) as applied to claims 1-2, 15-16 and 18-19 above, and further in view of document A Workload-Aware Adaptive Hybrid Flash Translation Layer with an Efficient Caching Strategy (hereinafter referred as Park et al.).
With respect claim 3, Palmer and Kim et al. do not teach wherein the target read/write type comprises a read task and a write task; and wherein in a case that the target read/write type is the write task, the second FTL algorithm comprises a DFTL algorithm; and in a case that the target read/write type is the read task, the second FTL algorithm comprises a BAN algorithm.
However, Park et al. teaches wherein when there are frequently read access, FTL converts this type of cold data blocks to a block level mapping (see page 251, right column, lines 12-32); and if there exist many invalid pages in a block due to frequent updates, we cannot take advantage of direct address translation of a block level mapping scheme because additional accesses are required to look up the valid data pages. To reduce this extra overhead and exploit the benefit (i.e., good write performance) of a page level mapping, CFTL manages those kinds of data with a page level mapping (see page 251, right column, lines 47-56; and page 252, left column, lines 1-8).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Kim et al. to include the above mentioned to achieve good write and read performance (see Park, page 249, left column, lines 50-56).
With respect claim 4, Palmer and Kim et al. do not teach wherein the target read/write type comprises a sequential read task, a sequential write task, a random write task, and a random read task; and wherein in a case that the target read/write type is the sequential read task or the random read task, the second FTL algorithm comprises a BAN algorithm; in a case that the target read/write type is the sequential write task, the second FTL algorithm comprises a FAST algorithm; and in a case that the target read/write type is the random write task, the second FTL algorithm comprises a DFTL algorithm.
However, Park et al. teaches wherein when there are frequently read access, FTL converts this type of cold data blocks to a block level mapping (see page 251, right column, lines 12-32); and if there exist many invalid pages in a block due to frequent updates, we cannot take advantage of direct address translation of a block level mapping scheme because additional accesses are required to look up the valid data pages. To reduce this extra overhead and exploit the benefit (i.e., good write performance) of a page level mapping, CFTL manages those kinds of data with a page level mapping (see page 251, right column, lines 47-56; and page 252, left column, lines 1-8).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Kim et al. to include the above mentioned to achieve good write and read performance (see Park, page 249, left column, lines 50-56).
With respect claim 17, Palmer and Kim et al. do not teach wherein the target read/write type comprises a read task and a write task; and wherein in a case that the target read/write type is the write task, the second FTL algorithm comprises a DFTL algorithm; and in a case that the target read/write type is the read task, the second FTL algorithm comprises a BAN algorithm.
However, Park et al. teaches wherein when there are frequently read access, FTL converts this type of cold data blocks to a block level mapping (see page 251, right column, lines 12-32); and if there exist many invalid pages in a block due to frequent updates, we cannot take advantage of direct address translation of a block level mapping scheme because additional accesses are required to look up the valid data pages. To reduce this extra overhead and exploit the benefit (i.e., good write performance) of a page level mapping, CFTL manages those kinds of data with a page level mapping (see page 251, right column, lines 47-56; and page 252, left column, lines 1-8).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Kim et al. to include the above mentioned to achieve good write and read performance (see Park, page 249, left column, lines 50-56).
With respect claim 20, Palmer and Kim et al. do not teach wherein the target read/write type comprises a read task and a write task; and wherein in a case that the target read/write type is the write task, the second FTL algorithm comprises a DFTL algorithm; and in a case that the target read/write type is the read task, the second FTL algorithm comprises a BAN algorithm.
However, Park et al. teaches wherein when there are frequently read access, FTL converts this type of cold data blocks to a block level mapping (see page 251, right column, lines 12-32); and if there exist many invalid pages in a block due to frequent updates, we cannot take advantage of direct address translation of a block level mapping scheme because additional accesses are required to look up the valid data pages. To reduce this extra overhead and exploit the benefit (i.e., good write performance) of a page level mapping, CFTL manages those kinds of data with a page level mapping (see page 251, right column, lines 47-56; and page 252, left column, lines 1-8).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Palmer and Kim et al. to include the above mentioned to achieve good write and read performance (see Park, page 249, left column, lines 50-56).
Allowable Subject Matter
Claims 9-10 and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Seo (US2021/0357318) teaches a method of operating a memory controller that includes a first flash translation layer configured to control a first memory area and a second flash translation layer configured to control a second memory area… and transmitting the logical address to the first flash translation layer or the second flash translation layer selected according to the criterion selected between the first criterion and the second criterion (see paragraph 12).
Zhou (US2022/0129189) teaches wherein after receiving a write operation request, the flash device selects a target FTL from the FTLs based on the received write operation request and allocates a physical address from the flash device to the received write operation request based on the target FTL (see Abstract).
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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