CTNF 19/235,992 CTNF 82453 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Information Disclosure Statement The Information Disclosure Statement filed on 12 Jun 2025 has been considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-17 of U.S. Patent No. 12,332,776 contains every element of claims 1-20 of the instant application and as such anticipates claims 1-20 of the instant application. Claim Correspondence Instant Application U.S. Patent No. 12,332,776 1 1 2 1 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 7 11 9 12 7 13 7 14 7 15 14 16 14 17 1 18 14 19 3 20 15 Claims 17 and 19, directed to an apparatus, are rejected as being obvious in view of the method of U.S. Patent No. 12,332,776. “A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by , the earlier claim. In re Longi , 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg , 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001). 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non- structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. 07-30-06 This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “processing device” and “bypass component” in claims 9-20. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Objections 07-29-01 AIA Claim 9-14 objected to because of the following informalities: Examiner suggests amending line 8 of claim 9 to read “reduced credit value; and ”. Claims not referred to specifically are objected as depending from an objected claim . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1, 2, 4, 15, 16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boals et al. (Pub. No. US 2020/0174693) in view of Kon (U.S. Patent No. 6,249,838) . Claim 1: Boals et al. disclose a method, comprising: performing an erase operation across the block stripe [pars. 0018, 0024, 0026 – Erase operations are performed. (“The controller 115 can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N and other such operations.”)] ; However, Boals et al. do not specifically disclose, assigning a respective initial credit value to each LUN of a block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; and refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero. In the same field of endeavor, Kon discloses, assigning a respective initial credit value to each LUN of a block stripe [abstract – Counter is initialized. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] ; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value [abstract – Counter is decremented on each erasure. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] ; and refraining from programming to each LUN of the block stripe having a respective reduced credit value equal to zero [abstract – Memory is disabled when the counter reaches zero. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Boals et al. to include an erase counter, as taught by Kon, in order to track the lifetime of the memory. Claim 2 (as applied to claim 1 above): Boals et al. disclose the method, further including, programming to each LUN of the block stripe having a respective reduced credit value greater than zero [par. 0027 – Write operations are performed. (“A write operation can be performed on the received data in a manner where controller 115 stripes the data across the memory components 112. For instance, the data can be written on page 0 of block 0 of LUN 0, page 0 of block 0 of LUN 1, page 0 of block 0 of LUN 2, and so forth until the data has been written to memory components 112 in its entirety. The data that is striped across multiple LUNs can be referred to as a block stripe. Block striping can improve the performance of memory sub-system 110. For instance, concurrently writing across multiple LUNs can improve parallelism and improve the speed at which the memory components 112 can be written. It can be noted that for some implementations, no more than one memory operation can be performed on a single LUN at a given instance.”)] . Claim 4 (as applied to claim 1 above): Kon discloses, wherein the respective initial credit values have a plurality of values [abstract – Counters are initialized. As discussed above with respect to Suhler et al., each LUN has a counter. Examiner notes that the claim does not require that the plurality of values differ from each other. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] . Claim 15: Boals et al. disclose an apparatus, comprising: a memory system controller including a processing device and a bypass component coupled to a memory device, wherein the processing device and bypass component are configured to [figs. 1, 6 - controller] : perform an erase operation across the block stripe [pars. 0018, 0024, 0026 – Erase operations are performed. (“The controller 115 can communicate with the memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N and other such operations.”)] ; However, Boals et al. do not specifically disclose, wherein the processing device and bypass component are configured to: assign a respective initial credit value to each LUN of a block stripe; reduce, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; and refrain from programming to each LUN of the block stripe having a respective reduced credit value equal to zero. In the same field of endeavor, Kon discloses, wherein the processing device and bypass component are configured to: assign a respective initial credit value to each LUN of a block stripe [abstract – Counter is initialized. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] ; reduce, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value [abstract – Counter is decremented on each erasure. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] ; and refrain from programming to each LUN of the block stripe having a respective reduced credit value equal to zero [abstract – Memory is disabled when the counter reaches zero. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] . It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Boals et al. to include an erase counter, as taught by Kon, in order to track the lifetime of the memory. Claim 16 (as applied to claim 15 above): Boals et al. disclose, wherein the processing device and bypass component are configured to perform a programming operation on each LUN of the block stripe having a respective reduced credit value greater than zero [par. 0027 – Write operations are performed. (“A write operation can be performed on the received data in a manner where controller 115 stripes the data across the memory components 112. For instance, the data can be written on page 0 of block 0 of LUN 0, page 0 of block 0 of LUN 1, page 0 of block 0 of LUN 2, and so forth until the data has been written to memory components 112 in its entirety. The data that is striped across multiple LUNs can be referred to as a block stripe. Block striping can improve the performance of memory sub-system 110. For instance, concurrently writing across multiple LUNs can improve parallelism and improve the speed at which the memory components 112 can be written. It can be noted that for some implementations, no more than one memory operation can be performed on a single LUN at a given instance.”)] . Claim 18 (as applied to claim 15 above): Kon discloses, wherein the respective initial credit values have a plurality of values [abstract – Counters are initialized. As discussed above with respect to Suhler et al., each LUN has a counter. Examiner notes that the claim does not require that the plurality of values differ from each other. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] . Claim 20 (as applied to claim 18 above): Kon discloses, wherein the respective initial credit value of each LUN of the block stripe corresponds to a respective program erase count endurance of each LUN of the block stripe [abstract – Counter is initialized according to the number of maximum permissible erasures. (“In a flash memory embodiment, a counter initialized to the number of maximum permissible flash memory erasures is stored in a counter, such as in the header portion of the flash memory. The counter is decremented with each erasure and, as the counter approaches zero, appropriate actions can be taken such as warning the user, support personnel, vendor and the like and/or disabling the flash memory.”)] . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LARRY T. MACKALL Primary Examiner Art Unit 2131 13 June 2026 /LARRY T MACKALL/Primary Examiner, Art Unit 2139 Application/Control Number: 19/235,992 Page 2 Art Unit: 2139 Application/Control Number: 19/235,992 Page 3 Art Unit: 2139 Application/Control Number: 19/235,992 Page 4 Art Unit: 2139 Application/Control Number: 19/235,992 Page 5 Art Unit: 2139 Application/Control Number: 19/235,992 Page 6 Art Unit: 2139 Application/Control Number: 19/235,992 Page 7 Art Unit: 2139 Application/Control Number: 19/235,992 Page 8 Art Unit: 2139 Application/Control Number: 19/235,992 Page 9 Art Unit: 2139 Application/Control Number: 19/235,992 Page 10 Art Unit: 2139 Application/Control Number: 19/235,992 Page 11 Art Unit: 2139 Application/Control Number: 19/235,992 Page 12 Art Unit: 2139 Application/Control Number: 19/235,992 Page 13 Art Unit: 2139 Application/Control Number: 19/235,992 Page 14 Art Unit: 2139 Application/Control Number: 19/235,992 Page 15 Art Unit: 2139 Application/Control Number: 19/235,992 Page 16 Art Unit: 2139 Application/Control Number: 19/235,992 Page 17 Art Unit: 2139 Application/Control Number: 19/235,992 Page 18 Art Unit: 2139
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