DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 - 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12,354,556 in view of Yamazaki (US 2024/0087487 A1, Cited by the Examiner in parent application 18/362,493 and listed on the IDS filed August 07, 2025).
Regarding Claim 1 of the instant application, Claim 1 of US 12,354,556 B2 discloses “A thin film transistor substrate comprising: a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode; a second thin film transistor on the substrate, the second thin film transistor including a second active layer and a second gate electrode above the first active layer and the first gate electrode; a first insulating layer between the first gate electrode and the second active layer” (Claim 1, Column 21, Lines 17 – 28 ) and “a first connection electrode connecting together the first active layer and the second active layer, the first connection electrode extending through a first contact hole in the first insulating layer and is in contact with each of the first active layer and the second active layer” (Claim 1, Column 21, Lines 29 – 33). However, Claim 1 of US 12,354,556 fails to explicitly disclose
“a second insulating layer between the second active layer and the second gate electrode” and “wherein a top of the first connection electrode is provided under the second insulating layer”.
In a similar filed of endeavor, Yamazaki teaches “a second insulating layer between the second active layer and the second gate electrode” (Figure 13 (Notice that a bottommost thick layer of layer 40 provides a second insulating layer as described in relation to Figure 12 that between the second gate electrode of transistor 95 and the second active layer of transistor 95 from top to bottom to Figure 13 with the label “FIG. 13” running from left to right.)) and “wherein a top of the first connection electrode is provided under the second insulating layer” (Figure 13 (Notice that the leftmost conducting structure as described above is made of several portions (i.e. tapered portions with tops, capping portions with tops), where a top of at least one of the several portions of the leftmost conducting structure is provided at a level which is below/under the second insulating layer provided by the bottommost thick layer of layer 40 as described above.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “a second insulating layer between the second active layer and the second gate electrode” because one having ordinary skill in the art wound want to fill voids between transistors without causing shorting. In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “wherein a top of the first connection electrode is provided under the second insulating layer” because one having ordinary skill in the art wound want to provide a layered construction resulting in discontinuous filing of contact holes.
Regarding Claim 2 of the instant application, Claim 4 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 4 discloses “wherein a portion of a lower surface of the second active layer is in contact with a side surface and a portion of an upper surface of the first connection electrode” (Column 21, Claim 4, Lines 54 – 57).
Regarding Claim 3 of the instant application, Claim 5 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 5 discloses “wherein an end of the second active layer is in contact with a side surface of the first connection electrode” (Column 21, Claim 5, Lines 58 – 60).
Regarding Claim 4 of the instant application, Claim 6 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 6 discloses “wherein the second active layer is in contact with a first side of the first connection electrode, a second side of the first connection electrode that is opposite the first side, and an upper surface of the first connection electrode that is between the first side and the second side of the first connection electrode” (Column 21, Claim 6, Lines 61 – 67).
Regarding Claim 5 of the instant application, Claim 7 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 7 discloses “wherein the second thin film transistor further comprises: a second drain electrode in contact with the second active layer, wherein a first side of the second active layer is in contact with the first connection electrode and a second side of the second active layer that is opposite the first side of the second active layer is in contact with the second drain electrode, and an overlapping structure between the first side of the second active layer and the first connection electrode is different from an overlapping structure between the second side of the second active layer and the second drain electrode” (Column 22, Claim 7, Lines 1 – 14).
Regarding Claim 6 of the instant application, Claim 8 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 8 discloses “wherein each of the first active layer and the second active layer includes a channel part and a connection part connected to a side of the channel part, the connection part having an electrical conductivity that is greater than an electrical conductivity of the channel part, and the first connection electrode is in contact with the connection part of the first active layer and the connection part of the second active layer” (Column 22, Claim 8, Lines 15 – 23.)).
Regarding Claim 7 of the instant application, Claim 9 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 9 discloses “wherein the first connection electrode comprises a second source electrode of the second thin film transistor” (Column 22, Claim 9, Lines 24 – 26.)).
Regarding Claim 8 of the instant application, Claim 10 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 10 discloses “wherein the first connection electrode comprises the second active layer of the second thin film transistor” (Column 22, Claim 10, Lines 27 – 29.)).
Regarding Claim 9 of the instant application, Claim 11 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 11 discloses “wherein the second active layer includes a channel part and a connection part connected to a side of the channel part, the connection part having an electrical conductivity that is greater than an electrical conductivity of the channel part, and the first connection electrode is the connection part” (Column 22, Claim 11, Lines 30 – 35.)).
Regarding Claim 10 of the instant application, Claim 12 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 12 discloses “further comprising: a second source electrode in contact with an upper surface of the first connection electrode” (Column 22, Claim 12, Lines 36 – 39.)).
Regarding Claim 11 of the instant application, Claim 13 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 13 discloses “wherein the second thin film transistor further comprises: a second drain electrode in contact with the second active layer and the thin film transistor substrate further comprising: a bridge electrode on the second insulating layer, the bridge electrode electrically connected to the second drain electrode of the second thin film transistor through a second contact hole in the second insulating layer” (Column 22, Claim 13, Lines 40 – 50).
Regarding Claim 12 of the instant application, Claim 14 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 14 discloses “wherein the second contact hole overlaps the bridge electrode and the second drain electrode, and the second contact hole is non-overlapping with the second active layer.” (Column 22, Claim 14, Lines 51 – 54).
Regarding Claim 13 of the instant application, Claim 15 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 15 discloses “wherein the second contact hole overlaps the bridge electrode, the second drain electrode, and the second active layer” (Column 22, Claim 15, Lines 55 – 58).
Regarding Claim 14 of the instant application, Claim 17 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 17 discloses “further comprising: a first capacitor electrode electrically connected to the second gate electrode and the first capacitor electrode on a same layer as the second gate electrode; and a second capacitor electrode on a same layer as the first connection electrode” (Column 23, Claim 17, Lines 18 – 24).
Regarding Claim 15 of the instant application, Claim 18 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 18 discloses “wherein the first gate electrode, the second gate electrode, the first active layer, and the second active layer overlap each other” (Column 23, Claim 18, Lines 25 – 28).
Regarding Claim 16 of the instant application, Claim 20 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 20 discloses “wherein a gate driver and an active array are on the substrate, the active array is farther from the substrate than the gate driver and the active array overlaps the gate driver, the gate driver includes a shift register including a pull-up transistor configured to output a gate-on signal and a pull-down transistor configured to output a gate-off signal, and the first thin film transistor and the second thin film transistor are connected in parallel to collectively form the pull-up transistor, or the first thin film transistor and the second thin film transistor are connected in parallel to collectively form the pull-down transistor” (Column 23, Claim 20, Lines 42 - 54).
Regarding Claim 17 of the instant application, Claim 27 of US 12,354,556 B2 discloses “A display apparatus comprising: a substrate; a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode; a second thin film transistor on the substrate and including a second active layer and a second gate electrode, the second active layer electrically connected to the first active layer and farther from the substrate than the first active layer and the second gate electrode farther from the substrate than the first gate electrode; a first insulating layer between the first gate electrode and the second active layer” (Column 24, Claim 26, Lines 23 – 37), “a first connection electrode connecting together the first active layer and the second active layer” (Column 24, Claim 27, Lines 45 – 47), and “one or more pixels on the substrate, the one or more pixels configured to emit light” (Column 24, Claim 26, Lines 38 – 39). However, Claim 27 of US 12,354,556 fails to explicitly disclose “a second insulating layer between the second active layer and the second gate electrode” and “wherein a top of the first connection electrode is provided under the second insulating layer”.
In a similar filed of endeavor, Yamazaki teaches “a second insulating layer between the second active layer and the second gate electrode” (Figure 13 (Notice that a bottommost thick layer of layer 40 provides a second insulating layer as described in relation to Figure 12 that between the second gate electrode of transistor 95 and the second active layer of transistor 95 from top to bottom to Figure 13 with the label “FIG. 13” running from left to right.)) and “wherein a top of the first connection electrode is provided under the second insulating layer” (Figure 13 (Notice that the leftmost conducting structure as described above is made of several portions (i.e. tapered portions with tops, capping portions with tops), where a top of at least one of the several portions of the leftmost conducting structure is provided at a level which is below/under the second insulating layer provided by the bottommost thick layer of layer 40 as described above.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “a second insulating layer between the second active layer and the second gate electrode” because one having ordinary skill in the art wound want to fill voids between transistors without causing shorting. In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “wherein a top of the first connection electrode is provided under the second insulating layer” because one having ordinary skill in the art wound want to provide a layered construction resulting in discontinuous filing of contact holes.
Regarding Claim 18 of the instant application, Claim 27 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. In addition, Claim 27 discloses “wherein the first connection electrode extends through a contact hole in the first insulating layer and in contact with each of the first active layer and the second active layer” (Column 24, Claim 27, Lines 45 – 50).
Regarding Claim 19 of the instant application, Claim 9 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. Specifically, Claims 1 and 9 of US 12,354,556 B2 provide for everything except the substrate being part of a “display apparatus”, “a second insulating layer between the second active layer and the second gate electrode”, “one or more pixels on the substrate, the one or more pixels configured to emit light”, and “wherein a top of the first connection electrode is under the second insulating layer”.
In a similar filed of endeavor, Yamazaki teaches the substrate being part of “display apparatus” (Figure 13, Items 70, 431, and Paragraphs [0297] (Notice that one or more pixels emitting light are providing via pixel circuitry 431 and light emitting elements 70 creating a display apparatus array of which a truncated version is shown.)), “a second insulating layer between the second active layer and the second gate electrode” (Figure 13 (Notice that a bottommost thick layer of layer 40 provides a second insulating layer as described in relation to Figure 12 that between the second gate electrode of transistor 95 and the second active layer of transistor 95 from top to bottom to Figure 13 with the label “FIG. 13” running from left to right.)), “one or more pixels on the substrate, the one or more pixels configured to emit light”, (Figure 13, Items 70, 431, and Paragraphs [0297] (Notice that one or more pixels emitting light are providing via pixel circuitry 431 and light emitting elements 70 creating a display apparatus array of which a truncated version is shown.)), and “wherein a top of the first connection electrode is provided under the second insulating layer” (Figure 13 (Notice that the leftmost conducting structure as described above is made of several portions (i.e. tapered portions with tops, capping portions with tops), where a top of at least one of the several portions of the leftmost conducting structure is provided at a level which is below/under the second insulating layer provided by the bottommost thick layer of layer 40 as described above.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “a second insulating layer between the second active layer and the second gate electrode” because one having ordinary skill in the art wound want to fill voids between transistors without causing shorting. In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “wherein a top of the first connection electrode is provided under the second insulating layer” because one having ordinary skill in the art wound want to provide a layered construction resulting in discontinuous filing of contact holes. Finally, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the substrate being part of a “display apparatus” and “one or more pixels on the substrate, the one or more pixels configured to emit light” because one having ordinary skill in the art wound want to provide image generation.
Regarding Claim 20 of the instant application, Claim 10 of US 12,354,556 B2 and Yamazaki disclose/ teach everything claimed as applied above. Specifically, Claims 1 and 10 of US 12,354,556 B2 provide for everything except the substrate being part of a “display apparatus”, “a second insulating layer between the second active layer and the second gate electrode”, “one or more pixels on the substrate, the one or more pixels configured to emit light”, and “wherein a top of the first connection electrode is under the second insulating layer”.
In a similar filed of endeavor, Yamazaki teaches the substrate being part of “display apparatus” (Figure 13, Items 70, 431, and Paragraphs [0297] (Notice that one or more pixels emitting light are providing via pixel circuitry 431 and light emitting elements 70 creating a display apparatus array of which a truncated version is shown.)), “a second insulating layer between the second active layer and the second gate electrode” (Figure 13 (Notice that a bottommost thick layer of layer 40 provides a second insulating layer as described in relation to Figure 12 that between the second gate electrode of transistor 95 and the second active layer of transistor 95 from top to bottom to Figure 13 with the label “FIG. 13” running from left to right.)), “one or more pixels on the substrate, the one or more pixels configured to emit light”, (Figure 13, Items 70, 431, and Paragraphs [0297] (Notice that one or more pixels emitting light are providing via pixel circuitry 431 and light emitting elements 70 creating a display apparatus array of which a truncated version is shown.)), and “wherein a top of the first connection electrode is provided under the second insulating layer” (Figure 13 (Notice that the leftmost conducting structure as described above is made of several portions (i.e. tapered portions with tops, capping portions with tops), where a top of at least one of the several portions of the leftmost conducting structure is provided at a level which is below/under the second insulating layer provided by the bottommost thick layer of layer 40 as described above.)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “a second insulating layer between the second active layer and the second gate electrode” because one having ordinary skill in the art wound want to fill voids between transistors without causing shorting. In addition, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide for “wherein a top of the first connection electrode is provided under the second insulating layer” because one having ordinary skill in the art wound want to provide a layered construction resulting in discontinuous filing of contact holes. Finally, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the substrate being part of a “display apparatus” and “one or more pixels on the substrate, the one or more pixels configured to emit light” because one having ordinary skill in the art wound want to provide image generation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 6, 11, 13, 15, and 17 – 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yamazaki (referenced in the Double Patenting rejections above).
Regarding Claim 1, Yamazaki discloses “A thin film transistor substrate comprising: a substrate” (Figure 13 and Paragraph [0296] (Notice that the bottom layer of Figure 13 corresponds to the substrate 701 labeled in Figure 12, where the bottom layer has thin film transistors 441 and 95.)), “a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode” (Figure 13 (Notice that transistor 441 provides a first thin film transistor on substrate 701 that includes a first active layer at its center under a first gate electrode at its center.)), “a second thin film transistor on the substrate, the second thin film transistor including a second active layer and a second gate electrode above the first active layer and the first gate electrode’ (Figure 13, Item 95 (Notice that transistor 95 provides a second thin film transistor on substrate 701 including a second active layer to its center below a second gate electrode at its center, where at the least the second gate electrode is above the first active layer and gate electrode of first thin film transistor 441 from top to bottom when Figure 13 is read with the label “FIG. 13” running from left to right.)), “a first insulating layer between the first gate electrode and the second active layer” (Figure 13 (Notice that at least one insulating layer provided by the thickest, topmost layer of layer 30 is between the first gate electrode of transistor 441 and the second active layer of transistor 95.)), “a second insulating layer between the second active layer and the second gate electrode” (Figure 13 (Notice that a bottommost thick layer of layer 40 provides a second insulating layer as described in relation to Figure 12 that between the second gate electrode of transistor 95 and the second active layer of transistor 95 from top to bottom to Figure 13 with the label “FIG. 13” running from left to right.)), “and a first connection electrode connecting together the first active layer and the second active layer, the first connection electrode extending through a first contact hole in the first insulating layer and is in contact with each of the first active layer and the second active layer” (Figure 13 (Notice the when viewing Figure 13 with the label “FIG. 13” running from left to right, a leftmost conducting structure provides a first connection electrode that extends through at least a first contact hole of the first described insulating layer, where the leftmost conducting structure is in electrical contact with each of the first active layer of transistor 441 and second active layer of 95 to connect each together.)), “wherein a top of the first connection electrode is provided under the second insulating layer” (Figure 13 (Notice that the leftmost conducting structure as described above is made of several portions (i.e. tapered portions with tops, capping portions with tops), where a top of at least one of the several portions of the leftmost conducting structure is provided at a level which is below/under the second insulating layer provided by the bottommost thick layer of layer 40 as described above.)).
Regarding Claim 2, Yamazaki discloses everything claimed as applied above (See Claim 1). In addition, Yamazaki discloses “wherein a portion of a lower surface of the second active layer is in contact with a side surface and a portion of an upper surface of the first connection electrode” (Figure 13 (Notice that a portion of a lower surface of the second active layer of transistor 95 is in electrical contact with a side surface and a portion of an upper surface of the first connection electrode provided by the leftmost conducting structure.)).
Regarding Claim 3, Yamazaki discloses everything claimed as applied above (See Claim 1). In addition, Yamazaki discloses “wherein an end of the second active layer is in contact with a side surface of the first connection electrode” (Figure 13 (Notice that an end of the second active layer of transistor 95 is in electrical contact with a side surface of the first connection electrode provided by the leftmost conducting structure.)).
Regarding Claim 4, Yamazaki discloses everything claimed as applied above (See Claim 1). In addition, Yamazaki discloses “wherein the second active layer is in contact with a first side of the first connection electrode, a second side of the first connection electrode that is opposite the first side, and an upper surface of the first connection electrode that is between the first side and the second side of the first connection electrode” (Figure 13 (Notice that the second active layer of transistor 95 is in electrical contact with first side surface of the first connection electrode, is in electrical contact with a second side surface of the first connection electrode that is opposite to the first, and in electrical contact with an upper surface existing between the first side and second side of the first connection electrode provided by the leftmost conducting structure.)).
Regarding Claim 5, Yamazaki discloses everything claimed as applied above (See Claim 1). In addition, Yamazaki discloses “wherein the second thin film transistor further comprises: a second drain electrode in contact with the second active layer” (Figure 13 (Notice that when Figure 13 is read with the label “FIG. 13” running from left to right, either the leftmost or rightmost region of the second active layer of transistor 95 provides a second drain electrode in contact with the second active layer.)), “wherein a first side of the second active layer is in contact with the first connection electrode” (Figure 13 (Notice that whether the leftmost or rightmost region is the drain electrode, each provides a first side of the second active layer that is in electrical contact with the leftmost conducting structure (first connection electrode).)), “and second side of the second active layer that is opposite the first side of the second active layer is in contact with the second drain electrode” ((Figure 13 (Notice that whether the leftmost or rightmost region is the drain electrode providing a first side, a second side opposite the first side of the second active layer is in electrical contact with the second drain electrode.)), “and an overlapping structure between the first side of the second active layer and the first connection electrode is different from an overlapping structure between the second side of the second active layer and the second drain electrode” (Notice that when the leftmost side is considered the first side of the active layer and second drain electrode, an overlapping structure of the horizontal conducting part (i.e. diagonal line portion in the middle of layer 40) between the first side and first connection electrode (leftmost conducting structure) is different from an overlapping insulation layer (i.e. insulating layer in layer 40) between the rightmost second side of the second active layer and defined second drain electrode. Also, notice that when the rightmost side is considered the first side of the active layer and second drain electrode, an overlapping structure of the horizontal conducting part (i.e. diagonal line portion in the middle of layer 40) between the first side and first connection electrode (leftmost conducting structure) is different from an overlapping insulation layer (i.e. insulating layer in layer 40) between the leftmost second side of the second active layer and defined second drain electrode.)).
Regarding Claim 6, Yamazaki discloses everything claimed as applied above (See Claim 1). In addition, Yamazaki discloses “wherein each of the first active layer and the second active layer includes a channel part and a connection part connected to a side of the channel part, the connection part having an electrical conductivity that is greater than an electrical conductivity of the channel part, and the first connection electrode is in contact with the connection part of the first active layer and the connection part of the second active layer” (Figures 12 – 13 and Paragraphs [0296], [0264] (Notice that each of the first active layer of transistor 441 and second active layer of transistor 95 includes a channel part and connection part with greater electrical conductivity to the side of the channel part, where the first connection part provide by the leftmost conducting structure is in electrical contact with the connection part of the first active layer and in electrical contact with the connection part of the second active layer.)).
Regarding Claim 11, Yamazaki discloses everything claimed as applied above (See Claim 1). In addition, Yamazaki discloses “wherein the second thin film transistor further comprises: a second drain electrode in contact with the second active layer” (Figure 13 (Notice that of the electrodes of the second thin film transistor 95, one of the right or left side (when viewing “FIG. 13” from left to right) has to be a second drain electrode (the other being the source) in physical and electrical contact with the second active layer.)), “and the thin film transistor substrate further comprising: a bridge electrode on the second insulating layer, the bridge electrode electrically connected to the second drain electrode of the second thin film transistor through a second contact hole in the second insulating layer” (Figure 13 (Notice that when the leftmost electrode of the second active layer is considered to be a second drain electrode, the bottommost thick layer of layer 40 provides a second insulating layer on the second active layer and a conductive structure above the leftmost electrode provides a bridge electrode on the defined second insulating layer where the bridge electrode is electrically connected to the defined second drain electrode via a contact hole in the second insulating layer that is above the leftmost electrode. Also, notice that when the rightmost electrode of the second active layer is considered to be a second drain electrode, the bottommost thick layer of layer 40 provides a second insulating layer on the second active layer and a second conductive structure above the rightmost electrode provides a bridge electrode on the defined second insulating layer where the bridge electrode is electrically connected to the defined second drain electrode via a contact hole in the second insulating layer that is above the rightmost electrode.)).
Regarding Claim 13, Yamazaki discloses everything claimed as applied above (See Claim 11). In addition, Yamazaki discloses “wherein the second contact hole overlaps the bridge electrode, the second drain electrode, and the second active layer” (Figure 13 (Notice the when either of the rightmost or leftmost electrode of the second active layer of transistor 95 is chosen as the second drain electrode, the second contact hole over the given electrode overlaps the bridge electrode, the second drain electrode, and the second active layer below it.)).
Regarding Claim 15, Yamazaki discloses everything claimed as applied above (See Claim 1). In addition, Yamazaki discloses “wherein the first gate electrode, the second gate electrode, the first active layer, and the second active layer overlap each other” (Figure 13 (Notice that when Figure 13 is read with the label “FIG. 13” running from left to right, a diagonal line cutting through the first gate electrode, the second gate electrode, the first active layer, and the second active provide a direction in which all overlap each other.)).
Regarding Claim 17, Yamazaki discloses “A display apparatus comprising: a substrate” (Figure 13 and Paragraph [0032] (Notice that a display apparatus is shown in Figure 13 with a bottommost substrate when the label “FIG. 13” is read from left to right.)), “a first thin film transistor on the substrate, the first thin film transistor including a first active layer and a first gate electrode” (Figure 13 (Notice that transistor 441 provided a first thin film transistor on the bottommost substrate (labeled as 701 in Figure 12) that includes a first active layer at its center under a first gate electrode at its center.)), “a second thin film transistor on the substrate and including a second active layer and a second gate electrode” (Figure 13, Item 95 (Notice that transistor 95 provides a second thin film transistor on the bottommost substrate including a second active layer to its center below a second gate electrode at its center.)), “the second active layer electrically connected to the first active layer and farther from the substrate than the first active layer and the second gate electrode farther from the substrate than the first gate electrode” (Figure 13 (Notice that the second active layer of transistor 95 is electrically connected to the first active layer of transistor 441 via a leftmost (i.e. when Figure 13 is read with label “FIG. 13” form left to right) conducting structure making contact through insulting layers and disposed in contact hole where the second active layer of transistor 95 is farther from the bottommost substrate than the first active layer of transistor 441 and the second gate electrode of transistor 95 is farther from the bottommost substrate than the first gate electrode of transistor 441.)), “a first insulating layer between the first gate electrode and the second active layer” (Figure 13 (Notice that at least one insulating layer provided by the thickest, topmost layer of layer 30 is between the first gate electrode of transistor 441 and the second active layer of transistor 95.)), “a second insulating layer between the second active layer and the second gate electrode” (Figure 13 (Notice that a bottommost thick layer of layer 40 provides a second insulating layer as described in relation to Figure 12 that between the second gate electrode of transistor 95 and the second active layer of transistor 95 from top to bottom to Figure 13 with the label “FIG. 13” running from left to right.)), “and a first connection electrode connecting together the first active layer and the second active layer” (Figure 13 (Notice the when viewing Figure 13 with the label “FIG. 13” running from left to right, a leftmost conducting structure provides a first connection electrode that extends through at least a first contact hole of the described first insulating layer, where the leftmost conducting structure is in electrical contact with each of the first active layer of transistor 441 and second active layer of 95 to connect each together.)), “one or more pixels on the substrate, the one or more pixels configured to emit light” (Figure 13, Items 70, 431, and Paragraphs [0297] (Notice that one or more pixels emitting light are providing via pixel circuitry 431 and light emitting elements 70 creating a display array of which a truncated version is shown.)), “wherein a top of the first connection electrode is provided under the second insulating layer” (Figure 13 (Notice that the leftmost conducting structure as described above is made of several portions (i.e. tapered portions with tops, capping portions with tops), where a top of at least one of the several portions of the leftmost conducting structure is provided at a level which is below/under the second insulating layer provided by the bottommost thick layer of layer 40 as described above.)).
Regarding Claim 18, Yamazaki discloses everything claimed as applied above (See Claim 17). In addition, Yamazaki discloses “wherein the first connection electrode extends through a contact hole in the first insulating layer and in contact with each of the first active layer and the second active layer” (Figure 13 (Notice the when viewing Figure 13 with the label “FIG. 13” running from left to right, the leftmost conducting structure provides a first connection electrode that extends through a contact hole of the first insulating layer provided by the thickest, topmost layer of layer 30, where the leftmost conducting structure is in electrical contact with each of the first active layer of transistor 441 and second active layer of 95 to connect each together.)).
Allowable Subject Matter
Claims 7 – 10, 12, 14, 16, and 19 - 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if all pertinent Double Patenting rejections made of record far above are overcome.
The subject matter of Claims 7 – 10, 12, 14, 16, and 19 – 20 including all limitations of each base claim and any intervening claims would be allowable over the prior art of record for reasoning reflected in the prosecution of parent application 18/362,493.
Conclusion
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/BRIAN M BUTCHER/Primary Examiner, Art Unit 2627 January 22, 2026