Prosecution Insights
Last updated: April 19, 2026
Application No. 19/236,212

SMART CARD FOR COMMUNICATION WITH AN EXTERNAL READER

Non-Final OA §102§103
Filed
Jun 12, 2025
Examiner
TARDIF, DAVID P
Art Unit
2876
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanide Holdings Pte. Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
82%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
373 granted / 519 resolved
+3.9% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
18 currently pending
Career history
537
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
59.4%
+19.4% vs TC avg
§102
31.5%
-8.5% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 519 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 06/12/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 1. Claims 1-14 and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Finn (9,195,932). As to claims 1 and 19: Finn teaches a smart card, comprising: a first coil having turns of wire defining a perimeter of a first surface area of the smart card and defining a first interior space within the first surface area surrounded by turns of wire of the first coil; a second coil having turns of wire defining a perimeter of a second surface area of the smart card and defining a second interior space within the second surface area surrounded by turns of wire of the second coil; a third coil having turns of wire defining a perimeter of a third surface area of the smart card and defining a third interior space within the third surface area surrounded by the wire of the third coil (figure 4B, 4E showing three antenna coils CC, EA, CA, all defining a specific interior space surrounded by the wire); and wherein the first second and third coils made from a single piece of wire, wherein a winding direction of the first coil is the same as a winding direction of the third coil (shown in figures 2A-2D, and figure 4I, wherein CC is envisioned to be either clockwise or counterclockwise as appropriate, and EA is shown as counterclockwise in 4I). As to claim 2: Finn teaches that the first, second, and third coils have the same winding direction (shown in figures 2A-2D, and figure 4I, wherein CC is envisioned to be either clockwise or counterclockwise as appropriate, and EA-1 and EA-2 is shown as counterclockwise in 4I). As to claim 3: Finn teaches that the second coil is arranged within the third interior space (figure 4H, 4I, wherein EA and CC lie within CA). As to claim 4: Finn teaches that the first coil is arranged within the third interior space (figure 4H, 4I, wherein EA and CC lie within CA). As to claim 5: Finn teaches that the first and second surface areas do not overlap one another (seen in figures 4H, 4I). As to claim 6: Finn teaches that the smart card comprises a microchip being connected to an integrated circuit (IC) system, wherein the first coil is arranged with respect to the IC module coil such that a magnetic field generated by the first coil can induce a current in the IC module coil, and wherein two wire ends of the second coil form a capacitive element, the capacitive element and the second coil forming an LC network, wherein the second coil is configured as a passive, non-radiating component of the LC network of matching the third coil with an external reader antenna (figure 9C, column 30, explains a chip CM which forms a circuit with capacitive elements MA1 and MA2, explained is the CA in figure 9A, the EA explained as a passive matching antenna for the BA resonant LC circuit, column 20, lines 25-60). As to claim 7: Finn teaches that the IC module coil and the first coil at least partially overlap (figure 15, figure 9A). As to claims 8 and 20: Finn teaches that the smart card comprises a non-metallic substrate, wherein the first second and third coils are laid into the non-metallic substrate via constant downward force for the duration of the wire embedding (column 29, first three paragraphs). As to claim 9: Finn teaches that the non-metallic substrate is defined as an antenna substrate which is disposed between a plurality of card substrate layers, wherein the antenna substrate is PET (column 43, lines 1-29, layers seen in figure 14D). As to claim 10: Finn teaches a smart card, comprising: a first coil having turns of wire defining a perimeter of a first surface area of the smart card and defining a first interior space within the first surface area surrounded by turns of wire of the first coil; a second coil having turns of wire defining a perimeter of a second surface area of the smart card and defining a second interior space within the second surface area surrounded by turns of wire of the second coil; a third coil having turns of wire defining a perimeter of a third surface area of the smart card and defining a third interior space within the third surface area surrounded by the wire of the third coil (figure 4B, 4E showing three antenna coils CC, EA, CA, all defining a specific interior space surrounded by the wire); and a microchip being connected to an integrated circuit (IC) system, wherein the first coil is arranged with respect to the IC module coil such that a magnetic field generated by the first coil can induce a current in the IC module coil, and wherein the third coil is electrically connected to the second coil and the first coil (seen in figures that show all three coils) wherein two wire ends of the second coil form a capacitive element, the capacitive element and the second coil forming an LC network, wherein the second coil is configured as a passive, non-radiating component of the LC network of matching the third coil with an external reader antenna (figure 9C, column 30, explains a chip CM which forms a circuit with capacitive elements MA1 and MA2, explained is the CA in figure 9A, the EA explained as a passive matching antenna for the BA resonant LC circuit, column 20, lines 25-60). As to claim 11: Finn teaches that the IC module coil is located on an IC module, wherein the IC module comprises a module substrate having terminal electrodes serving as contact-type transmission section, and wherein the IC module coil serves as a non-contact type transmission section (figure 1 showing the different layers of substrates that the coils are formed upon, figure 9C, column 30, explains a chip CM which forms a circuit with capacitive elements MA1 and MA2). As to claim 12: Finn teaches that the terminal electrodes and the IC module coil are formed on different surfaces of the module substrate by etching a double-sided copper-cladded module substrate (figure 1 showing the different layers of substrates that the coils are formed upon, metal foil taught to be copper, columns 43 and 44). As to claim 13: Finn teaches that the microchip is connected to the terminal electrodes of the module substrate via through-holes that are filled with a conductive material (figure 9B showing this). As to claim 14: Finn teaches that the microchip is connected to the IC module coil by wire bonding (column 29 explains wire bonding). As to claim 16: Finn teaches that the first coil, second coil and third coil are connected in parallel to each other (column 26). As to claim 17: Finn teaches that the first coil, the second coil and the third coil have different pitches (column 12, final two paragraphs). As to claim 18: Finn teaches that the first and second coils are arranged within the interior space of the third coil (figures 4H, 4I). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 2. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Finn (9,195,932) as applied to claim 10, and further in view of Halope (2009/0095415). The teachings of Finn are discussed above. As to claim 15: Finn teaches the limitations of claim 10. Finn is silent as to that the wire bonding and the microchip are encapsulated by dam-and-fill encapsulation material. Halope teaches that a wire bonding and the microchip are encapsulated by dam-and-fill encapsulation material (paragraphs 0024-0025, figures 1-3). It would have been obvious to one of ordinary skill in the art at the time to combine the teachings of Finn with the teachings of Halope so that a typical and well known encapsulation method is used, which reduces errors and failure due to movement and infiltration of material onto the bonding surfaces. It would not require undue testing to combine these ideas as encapsulation of wire-bonded terminals, antennas and ICs are well known in the art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID P TARDIF whose telephone number is (571)270-7810. The examiner can normally be reached on M-F 10:30-7:00. If the examiner cannot be reached by telephone, he can be reached through the following email address: david.tardif@uspto.gov If attempts to reach the examiner by telephone and email are unsuccessful, the examiner’s supervisor, Michael G Lee can be reached on (571)272-2398. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. DAVID TARDIF Examiner Art Unit 2876 /DAVID TARDIF/ Examiner, Art Unit 2876 david.tardif@uspto.gov /MICHAEL G LEE/Supervisory Patent Examiner, Art Unit 2876
Read full office action

Prosecution Timeline

Jun 12, 2025
Application Filed
Jan 22, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
82%
With Interview (+10.4%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 519 resolved cases by this examiner. Grant probability derived from career allow rate.

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