DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Allowable Subject Matter
Claim(s) 2-4, 9, 12, 13 and 16 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8, 10, 11, 14, 15 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Lee (US 2021/0055888).
In claim(s) 1, 11 and 18, Lee teaches:
A storage device comprising: a nonvolatile memory device including a plurality of planes and a plurality of page buffers respectively connected to the plurality of planes; Fig. 5 and [0083] The page buffers 140b1 to 140b4 may be separately provided to respectively correspond to the memory cell arrays of the planes PLN1 to PLN4.
and a storage controller configured to provide, to the nonvolatile memory device, a read command for reading data stored in the plurality of planes, Fig. 4 and [0073] The control logic circuit and voltage generator 130 may control the address decoder 120, the page buffer 140a, and the input/output circuit 150, based on a command CMD′ and a control signal CTRL received from the controller 1330.
provide, to the nonvolatile memory device, a first select chip pause command for instructing data output of a first plane of the plurality of planes, and Fig. 16 and [0157] In some cases, the controller 1330 may determine that a DMA read operation directed to the memory chip 1311 is required, and may issue a DMA read command to the memory chip 1311 (at a time point t31). To this end, the controller 1330 may communicate with the memory chip 1311 through the channel CH1 without intervention of the host 1100. Data of the memory cell array of the plane PLN1 may be output to the controller 1330 through the channel CH1.
provide, to the nonvolatile memory device, a second select chip pause command for pausing the data output of the first plane and instructing data output of a second plane of the plurality of planes. Fig. 16 and [0158] For example, while the controller 1330 processes an operation directed to the memory cell array of the plane PLN1, the controller 1330 may receive a read request directed to the memory chip 1312 from the host 1100 (at a time point t32). The controller 1330 may temporarily suspend the DMA read operation for the memory chip 1311 in response to the read request (at a time point t33). [0159] As the operation directed to the memory cell array of the plane PLN1 is partially processed and suspended, the controller 1330 may transmit a read command associated with the read request received at the time point t32 to the memory chip 1312 through the channel CH1 (at a time point t34).
In claim(s) 8 and 19, Lee teaches:
wherein the storage controller is configured to provide the second select chip pause
command to the nonvolatile memory device via a command/address line based on receiving data of the first plane from the nonvolatile memory device via a data line. Fig. 16 and [0158] For example, while the controller 1330 processes an operation directed to the memory cell array of the plane PLN1, the controller 1330 may receive a read request directed to the memory chip 1312 from the host 1100 (at a time point t32). The controller 1330 may temporarily suspend the DMA read operation for the memory chip 1311 in response to the read request (at a time point t33). [0159] As the operation directed to the memory cell array of the plane PLN1 is partially processed and suspended, the controller 1330 may transmit a read command associated with the read request received at the time point t32 to the memory chip 1312 through the channel CH1 (at a time point t34). Fig. 4 and [0073] The control logic circuit and voltage generator 130 may control the address decoder 120, the page buffer 140a, and the input/output circuit 150, based on a command CMD′ and a control signal CTRL received from the controller 1330.
In claim(s) 10, Lee teaches:
wherein the nonvolatile memory device is configured to store, in the page buffers, data that first device, the first data in response to a select chip enable command received before the first select chip pause command. [0076] The page buffer 140a may temporarily store data received from the input/output circuit 150 and data read from the memory cell array 110a. For example, the page buffer 140a may include data latches for storing data.
In claim(s) 14, Lee teaches:
wherein the control logic circuit is configured to control the page buffers to output, to the first device, the first data in response to a select chip enable command received before the first select chip pause command. [0043] the host 1100 may provide the storage device 1300 with the command CMD including a read request. The storage device 1300 may output requested read data to the host 1100 during a read operation, in response to the read request.
In claim(s) 15, Lee teaches:
wherein the control logic circuit is configured to, in response to a second select chip pause command received after the first select chip pause command, control the page buffers to pause the output of the second data and output, to the first device, third data stored in a third page buffer of the plurality of page buffers the third page buffer being connected to a third plane of the plurality of planes. Fig. 16 and [0158] For example, while the controller 1330 processes an operation directed to the memory cell array of the plane PLN1, the controller 1330 may receive a read request directed to the memory chip 1312 from the host 1100 (at a time point t32). The controller 1330 may temporarily suspend the DMA read operation for the memory chip 1311 in response to the read request (at a time point t33). [0159] As the operation directed to the memory cell array of the plane PLN1 is partially processed and suspended, the controller 1330 may transmit a read command associated with the read request received at the time point t32 to the memory chip 1312 through the channel CH1 (at a time point t34). Lee does not explicitly teach “third select chip pause command”, however, having more than two chip pause command instead more than one does not produce new and unexpected result, as of the effective filing date of the application. Therefore this is duplication of parts which has no patentable significance. See In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
In claim(s) 17, Lee teaches:
wherein the control logic circuit is configured to receive the first select chip pause command via a command/address line, and the page buffers are configured to output the first data or the second data to the first device via a data line. [0043] For example, the host 1100 may provide the storage device 1300 with the command CMD including a write request and the data DAT including write data. The storage device 1300 may store the requested write data during a write operation, in response to the write request. For example, the host 1100 may provide the storage device 1300 with the command CMD including a read request. The storage device 1300 may output requested read data to the host 1100 during a read operation, in response to the read request.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0055888) in view of Li (US 2026/0178228).
In claim(s) 5, Lee does not explicitly but Li teaches:
wherein the first select chip pause command includes first select chip enable data for
instructing data output and a first plane index for selecting the first plane to output data. [0011] obtaining physical characteristics of the physical address of the read command according to the physical address of the read command, wherein the physical characteristics include the chip enable pin, the plane, a chip.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to combine the storage system/method of Lee with the data storage/retrieval system/method of Li. The rationale for doing so would have been that use of location information including chip and plane in a memory command in a memory would provide a reliable, well-known means to reliably and efficiently control/perform data storage/retrieval in the memory with a reasonable expectation of success.
In claim(s) 6, Li teaches:
wherein the nonvolatile memory device is configured to: select the first plane based on the first plane index; [0011] obtaining physical characteristics of the physical address of the read command according to the physical address of the read command, wherein the physical characteristics include the chip enable pin, the plane, a chip.
Lee teaches and output, to the storage controller and based on the first select chip enable data, first data stored in a first page buffer of the plurality of page buffers that is connected to the first plane. [0076] The page buffer 140a may temporarily store data received from the input/output circuit 150 and data read from the memory cell array 110a. For example, the page buffer 140a may include data latches for storing data. [0077] Alternatively, the input/output circuit 150 may provide the controller 1330 with data received from the page buffer 140a.
Claim(s) 7 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0055888) in view of Bae (US 2021/0133096).
In claim(s) 7 and 20, Lee teaches:
wherein the storage controller is configured to: provide, to the nonvolatile memory device, a third select chip pause command for pausing the data output of the second plane and instructing data output of a third plane of the plurality of planes; and provide, to the nonvolatile memory device, Fig. 16 and [0158] For example, while the controller 1330 processes an operation directed to the memory cell array of the plane PLN1, the controller 1330 may receive a read request directed to the memory chip 1312 from the host 1100 (at a time point t32). The controller 1330 may temporarily suspend the DMA read operation for the memory chip 1311 in response to the read request (at a time point t33). [0159] As the operation directed to the memory cell array of the plane PLN1 is partially processed and suspended, the controller 1330 may transmit a read command associated with the read request received at the time point t32 to the memory chip 1312 through the channel CH1 (at a time point t34). Lee does not explicitly teach “third select chip pause command”, however, having more than two chip pause command instead more than one does not produce new and unexpected result, as of the effective filing date of the application. Therefore this is duplication of parts which has no patentable significance. See In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Lee does not explicitly teach, but Bae teaches a select chip terminate command for terminating data output of the nonvolatile memory device. [0064] when the first memory chip is performing a read operation for data different from the first data, controller 100 may read the first data from the first memory chip after the read operation is terminated.
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the invention, to combine the storage system/method of Lee with the memory system operation method of Bae. The rationale for doing so would have been that use of data i/o termination signal in a memory system would provide a reliable, well-known means to provide a reliable data storage/retrieval trafficking in the memory system with a reasonable expectation of success.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Farmahini (US 2021/0223985): discloses data processing on memory controller.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES J CHOI whose telephone number is (571)270-0605. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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/CHARLES J CHOI/Primary Examiner, Art Unit 2133
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