DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 12 June 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 10-11, and 12-14 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Xu (US 20210334200 A1).
Referring to claims 1, 10, and 12, taking claim 1 as exemplary, Xu teaches
A memory system, including: a host including a memory, ([Xu abstract, 0023, 0039, Fig. 1] The computing system 100 can include a host system 120 that is coupled to one or more memory sub-systems 110 and host memory buffer (HMB) 127 residing on the host memory device 125) the memory storing a logical address to physical address mapping (L2P) table; ([Xu abstract, 0015-0018, 0043] The mapping data structure, which is referred to as a logical-to-physical (L2P) map, can be stored by the memory sub-system. In order to reduce the access latency, at least a portion of the L2P map can be stored in a host memory buffer (HMB), which is dedicated by the host for use by the memory sub-system.) and a memory controller coupled to the host, the memory controller including a host interface controller and a controller processor; ([Xu 0030-0031, 0033, Fig. 1] A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130, 140 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations. The memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in a local memory 119. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130 as well as convert responses associated with the memory devices 130 into information for the host system 120.) wherein the host interface controller is configured to: receive an operation command from the host; ([Xu 0014, 0030] The memory sub-system can perform host-initiated data operations (e.g., write, read, erase, etc.). The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system and to read data from the memory device on the memory sub-system. A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130, 140 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations.) receive a logical address translation request sent by the controller processor in response to the operation command, wherein the logical address translation request includes a logical address; ([Xu 0015, 0033, 0037] The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130. the host system 120 identifies memory blocks by their respective logical block addresses (LBAs). In order to isolate from the host system various aspects of physical implementations of memory devices 130, 140 employed by the memory sub-system 110, the memory sub-system 110 can maintain an L2P map that maps each LBA to a corresponding physical address (PA).) retrieve a physical address corresponding to the logical address from the logical address to physical address mapping table, wherein the logical address to physical address mapping table is obtained by the host interface controller from the memory of the host; ([Xu 0068-0070, Fig. 7] FIG. 7 is a flow diagram of an example method of retrieving the translation layer metadata from the host memory buffer for performing a memory access operation, in accordance with aspects of the present disclosure. The method 700 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 700 is performed by the HMB management component 113 of FIG. 1. At operation 720, the processing device implementing the method receives, from the host system, the specified slot of the HMB containing translation layer metadata translation layer metadata and associated protection metadata. The translation layer metadata includes one or more L2P records, such that each L2P record maps a logical block address to a physical address identifying a memory block in the memory sub-system, as described in more detail herein above.) and send the physical address to the controller processor ([Xu 0072, Fig. 7] At operation 760, the processing device utilizes the translation layer metadata for performing a memory access operation (e.g., a read or write operation with respect to a memory location identified by the physical address specified by one or more L2P records contained by the translation layer metadata), and the method terminates.).
Referring to claims 2, 11, and 13, taking claim 2 as exemplary, Xu teaches
The memory system of claim 1, wherein the memory of the host includes a host memory buffer (HMB) storing the logical address to physical address mapping table therein, ([Xu 0017-0018, 0043] the L2P map can be stored in a host memory buffer (HMB)) and the host interface controller is further configured to: obtain the logical address to physical address mapping table from the host memory buffer through direct memory access ([Xu 0023] The computing system 100 can include a host system 120 that is coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory sub-system 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.).
Referring to claims 3 and 14, taking claim 3 as exemplary, Xu teaches
The memory system of claim 2, wherein the host interface controller is further configured to: perform a cyclic redundancy check on the logical address to physical address mapping table in response to obtaining the logical address to physical address mapping table from the host memory buffer ([Xu 0045, 0071, claim 11, Fig. 7] Responsive to successfully validating, at operation 730, the translation layer metadata, the processing device may, at operation 740, store the translation layer metadata on a volatile memory device of the memory system. Validating the translation layer metadata may involve computing the CRC parity of the translation layer metadata and compare the computed value to the CRC value stored by the protection metadata. Should the two values fail to match, the corresponding metadata block retrieved from the HMB is discarded, an exception is thrown at operation 750, and a corresponding error code is returned. Otherwise, if the computed CRC parity of the translation layer metadata retrieved from the HMB matches the CRC value stored by the protection metadata, the processing continues at operation 760.).
Referring to claims 4 and 15, taking claim 4 as exemplary, Xu teaches
The memory system of claim 2, wherein the logical address to physical address mapping table includes a plurality of sections, the host interface controller configured to: obtain one or more sections of the logical address to physical address mapping table from the host memory buffer ([Xu 0070, Fig. 7] At operation 720, the processing device implementing the method receives, from the host system, the specified slot of the HMB containing translation layer metadata translation layer metadata and associated protection metadata. The translation layer metadata includes one or more L2P records, such that each L2P record maps a logical block address to a physical address identifying a memory block in the memory sub-system, as described in more detail herein above.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 9, 16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 20210334200 A1) as applied to claims 1 and 12 above, and further in view of Wu (US 20240070081 A1).
Referring to claims 5 and 16, taking claim 5 as exemplary, Xu teaches
The memory system of claim 4 ([see above]).
Xu does not explicitly teach wherein the host interface controller is configured to: determine a section number of the logical address in the logical address to physical address mapping table; and obtain a corresponding section in the logical address to physical address mapping table from the host memory buffer according to the section number. Xu does disclose translation layer metadata comprising one or more logical-to-physical (L2P) records, wherein an L2P record of the one or more L2P records maps a logical block address to a physical address identifying a memory block in the memory system ([Xu abstract]).
Wu teaches wherein the host interface controller is configured to: determine a section number of the logical address in the logical address to physical address mapping table; ([Wu abstract, 0010, 0025, Fig. 1] metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, the metadata comprises a section number and a way number) and obtain a corresponding section in the logical address to physical address mapping table from the host memory buffer according to the section number ([Wu 0006, abstract, 0025, Fig. 1] system of using HMB as the cache of storage device physical address mapping table, which defines a management scheme for the L2P mapping table according to the use characteristics of the HMB for L2P entries, and realizes fast reading, writing, searching and real-time updating of the L2P mapping entries in the HMB. metadata calculation module, configured to calculate a metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, wherein the metadata comprises a section number and a way number, the section number is equal to a modulo result of dividing the logical address by the HMB size, and the way number is equal to a remainder of the modulo result divided by the number of ways).
Xu and Wu are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Xu and Wu before him or her to modify the system of Xu to include the HMB and L2P management scheme of Wu, thereafter the system is connected to HMB and L2P management scheme. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system to have improved management efficiency of the HMB and system as suggested by Wu. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Xu with Wu to obtain the invention as specified in the instant application claims.
Referring to claims 9 and 20, taking claim 9 as exemplary, Xu teaches
The memory system of claim 2 ([see above]).
Xu does not explicitly teach wherein the host interface controller is further configured to: report a HMB characteristic and a required storage space size to the host after a system being powered on; and send the logical address to physical address mapping table obtained from a memory device to the host, the host to store the logical address to physical address mapping table in the host memory buffer.
Wu teaches wherein the host interface controller is further configured to: report a HMB characteristic and a required storage space size to the host after a system being powered on; and send the logical address to physical address mapping table obtained from a memory device to the host, the host to store the logical address to physical address mapping table in the host memory buffer ([Wu 0006, abstract, 0025, Fig. 1] system of using HMB as the cache of storage device physical address mapping table, which defines a management scheme for the L2P mapping table according to the use characteristics of the HMB for L2P entries, and realizes fast reading, writing, searching and real-time updating of the L2P mapping entries in the HMB. metadata calculation module, configured to calculate a metadata according to logical address corresponding to the first entry of the table unit to be stored and the HMB size, wherein the metadata comprises a section number and a way number, the section number is equal to a modulo result of dividing the logical address by the HMB size, and the way number is equal to a remainder of the modulo result divided by the number of ways).
Xu and Wu are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Xu and Wu before him or her to modify the system of Xu to include the HMB and L2P management scheme of Wu, thereafter the system is connected to HMB and L2P management scheme. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system to have improved management efficiency of the HMB and system as suggested by Wu. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Xu with Wu to obtain the invention as specified in the instant application claims.
Claim(s) 8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (US 20210334200 A1) as applied to claims 1 and 12 above, and further in view of Benisty (US 20190250850 A1).
Referring to claims 8 and 19, taking claim 8 as exemplary, Xu teaches
The memory system of claim 1, wherein prior to receiving the logical address translation request from the controller processor, the host interface controller is further configured to ([see above]).
Xu does not explicitly teach parse the operation command; and place the parsed operation command into a command queue of the memory controller.
Benisty teaches parse the operation command; and place the parsed operation command into a command queue of the memory controller ([Benisty 0047-0048, 0060, 0074 Fig. 2A] The host system 140 has one or more processor(s) 150 and host memory 160. In one embodiment, host memory 160 includes command submission queues (SQs) 162 and command completion queues (CQs) 164. Commands to access the memory structure 126 in the memory die 108 may be placed by the host into a command submission queue 162. A host queue manager 246 is configured to fetch and parse commands from the command submission queue 162. The host queue manager 246 may also queue the commands internally (i.e., within the memory controller 122) for execution. In one embodiment, the host queue manager 246 determines when to send a command from the internal queue (within the memory controller 122) to a command executer 228 within a backend module 210 of the memory controller 122.).
Xu and Benisty are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Xu and Benisty before him or her to modify the system of Xu to include the queues and queue management of Benisty, thereafter the system is connected to queues and queue management. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system to allow the host to directly write to the memory controllers internal space as suggested by Benisty. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Xu with Wu to obtain the invention as specified in the instant application claims.
Allowable Subject Matter
Claims 6-7 and 17-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding host memory buffers.
US 20170300246 A1
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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