DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 19/236,687 has a total of 20 elected claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
INFORMATION CONCERNING DRAWINGS
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statement 06/12/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-9 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brewer et al. (US pub. 2003/0229739), hereinafter, “Brewer”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 11 and 16, Brewer discloses an interface circuit (system of fig. 2), including: a first communication circuit (bus protocol I/O unit 36) configured to communicate with an external device (a connector and a device having a compatible protocol that’s connected to protocol adapter 62; see paragraph 0027, which discloses “alternatively, a protocol adapter 62 connects at one end to universal protocol socket 48 and to the other end to a connector of a device having a compatible protocol. In this manner, a single set of routed lines, bus 50, to run through a motherboard and support multiple protocols, thus reducing line routing design problems”) based on a first protocol (see paragraph 0025, which discloses “referring now to FIG. 2, a block diagram depicts a bus protocol selector system 34 configured as an I/O interface chip 34. Plural bus protocol I/O units 36 and 38 each include logic for communicating information by using an associated bus protocol. For instance, bus protocol I/O unit 36 supports USB protocol to communicate with a bus protocol socket 40 having a USB form factor with the communication transferred over a differential serial bus 44. Similarly, bus protocol I/O unit 38 supports SATA protocol to communicate with a bus protocol socket 42 having a SATA form factor with the communication transferred over a differential serial bus 46. Thus, bus protocol socket 40 is a dedicated USB connector and bus protocol socket 42 is a dedicated SATA connector, each having an appropriate form factor to prevent user confusion regarding the devices that are appropriate for the bus. Information received from devices is translated by bus protocol I/O units 36 and 38 for transfer through chipset 22 of information handling system 10”); a second communication circuit (bus protocol I/O unit 38) configured to communicate with the external device based on a second protocol (see paragraph 0025); and a switching circuit (protocol selector unit 52 combined with universal protocol socket 48) coupled to the first communication circuit and the second communication circuit and configured to enable the first communication circuit or the second communication circuit (see paragraph 0026, which discloses “protocol selector unit 52 switches bus 50 to connect with bus 54 if a USB device is interfaced with universal protocol socket 48, and switches bus 50 to connect with bus 56 if a SATA device is interfaced with universal protocol socket 48”).
3. As per claims 2 and 17, Brewer discloses “The interface circuit of claim 1” [See rejection to claim 1 above], wherein the switching circuit is configured to: in response to receiving a first indication signal from the external device, enable the first communication circuit and disable the second communication circuit; and in response to receiving a second indication signal from the external device, enable the second communication circuit and disable the first communication circuit (see paragraph 0026).
4. As per claim 3, Brewer discloses wherein the switching circuit includes: a detection circuit (universal protocol socket 48) coupled to the external device and configured to detect the first indication signal and the second indication signal sent by the external device; and a control circuit (protocol selector unit 52) coupled to the detection circuit and configured to enable the first communication circuit or the second communication circuit based on a signal detected by the detection circuit (see paragraph 0026).
5. As per claims 4, 12 and 18, Brewer discloses wherein the detection circuit includes: a first detection circuit (capacitor 68 of fig. 3) configured to, in response to the first indication signal, output a first detection signal (see paragraphs 0027 and 0029); and a second detection circuit (bypass switch 66) configured to, in response to the second indication signal, output a second detection signal (see paragraphs 0027 and 0029), wherein the control circuit is configured to: in response to receiving the first detection signal, enable the first communication circuit and disable the second communication circuit; and in response to receiving the second detection signal, enable the second communication circuit and disable the first communication circuit (see paragraphs 0027, 0029 and 0030).
6. As per claims 5, 13 and 19, Brewer discloses, further including: an interface pad (protocol adapter 62) coupled to the external device (see paragraph 0027); and a selection circuit (protocol identification unit 58) coupled to the interface pad, the first communication circuit and the second communication circuit, wherein the selection circuit is configured to gate a first signal path between the first communication circuit and the interface pad or a second signal path between the second communication circuit and the interface pad (see paragraph 0026).
7. As per claim 6, Brewer discloses wherein the switching circuit is coupled to the selection circuit and is further configured to: in response to receiving the first indication signal, control the selection circuit to gate the first signal path; and in response to receiving the second indication signal, control the selection circuit to gate the second signal path (see paragraph 0026).
8. As per claim 7, Brewer discloses, further including a power management circuit coupled to the interface pad and configured to provide a first power supply voltage or a second power supply voltage to the interface pad (see paragraphs 0029 and 0030).
9. As per claims 8, 14 and 20, Brewer discloses wherein the switching circuit is coupled to the power management circuit and is further configured to: in response to receiving the first indication signal, control the power management circuit to provide the first power supply voltage to the interface pad; and in response to receiving the second indication signal, control the power management circuit to provide the second power supply voltage to the interface pad (see paragraphs 0029 and 0030).
10. As per claims 9 and 15, Brewer discloses wherein the first indication signal and the second indication signal meet a specification requirement of the first protocol, or wherein the first indication signal and the second indication signal meet a specification requirement of the second protocol (see paragraphs 0029 and 0030).
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim 10 are rejected under 35 U.S.C. 103(a) as being unpatentable over Brewer et al. (US pub. 2003/0229739), hereinafter, “Brewer”, in view of Jurski et al. (US pub. 2021/0318981), hereinafter, “Jurski”.
13. As per claim 10, Brewer discloses “The interface circuit of claim 1” [See rejection to claim 1 above], but fails to specifically disclose wherein the first protocol is a SMBus protocol and the second protocol is an I3C protocol, wherein the first indication signal includes a reset signal, and wherein the second indication signal includes a Ox7E broadcast address.
Jurski discloses wherein the first protocol is a SMBus protocol and the second protocol is an I3C protocol, wherein the first indication signal includes a reset signal, and wherein the second indication signal includes a Ox7E broadcast address (see paragraphs 0120 and 0266).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Jurski’s teaching of a controller device to detect an event indicating that a servant device is to be connected to a system management bus and in response to perform a selection process to choose between first and second communication protocols, into Brewer’s teaching of a bus protocol selector operable to select one of a plural bus protocols associated with a device interfaced with an information handling system and to communicate information over the bus with the selected bus protocol, for the benefit of providing auto-detection and compatibility with devices that use different protocols without loss of functionality.
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181
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