DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-9, 11, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US 2016/0104407) in view of Lee et al. (US 2016/0148570) and further in view of Jang et al. (US 2012/0127145).
Regarding claim 1:
Hong discloses:
Claim 1
Hong
1. (Currently Amended) A display device, comprising:
a display panel; and
abstract
a timing controller electrically connected to the display panel and configured to acquire a display control signal,
Fig. 3: 121; paragraph 84
wherein the timing controller is configured to determine whether the display control signal is abnormal, and is configured to output a feedback signal when the display control signal is abnormal;
Paragraph 84, where these detect an abnormality as per paragraphs 88-92
wherein the display control signal comprises a plurality of display control sub-signals, the feedback signal comprises a plurality of feedback sub-signals each corresponding to a respective one of the plurality of display control sub-signals; and
Paragraphs 88-92, where the error signal EDATA is a plurality of feedback sub-signals as shown in Fig. 7; Paragraphs 124-126
the timing controller is configured to determine whether the plurality of display control sub-signals are abnormal, and is configured to output a corresponding one of the plurality of feedback sub-signals when one of the plurality of display control sub-signals is abnormal;
Paragraphs 88-92, where the error signal EDATA is a plurality of feedback sub-signals as shown in Fig. 7; Paragraphs 124-126
wherein the plurality of display control sub-signals comprise:
a power signal configured to supply power to the timing controller; and
Paragraph 86: "normal level of a voltage," but this is the voltage from the power generator and it is not explicitly clear this supplies power for the timing controller
an image signal configured for the timing controller to control the display panel to display an image;
There are a variety of image signals including DCS, R'G'B' and GCS, but these are not directly tested for abnormality.
wherein the timing controller comprises:
a first register, wherein at least part of information stored in the first register is set by the timing controller as a first information when the image signal is abnormal, and one of the plurality of feedback sub-signals corresponding to the image signal comprises the first information; and
The image signal itself as now defined are not directly tested for abnormality.
a second register, wherein at least part of information stored in the second register is set by the timing controller as a second information when the power signal is abnormal, and one of the plurality of feedback sub-signals corresponding to the power signal comprises the second information.
EDATA as shown in Fig. 7, except, again, this power signal is slightly different that "the power signal" above
Therefore Hong does not disclose:
(A) "a power signal configured to supply power to the timing controller,"
(B) "a first register, wherein at least part of information stored in the first register is set by the timing controller as a first information when the image signal is abnormal, and one of the plurality of feedback sub-signals corresponding to the image signal comprises the first information"
Regarding (A):
Lee discloses:
a power supplier is included in the timing controller (paragraph 26)
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Hong a power signal configured to supply power to the timing controller, as suggested by Lee.
The rationale is as follows:
Hong and Lee are directed to the same field of art.
Hong has a power signal and tests it for abnormalities, but this test takes place in the power generator and not the timing controller. Lee teaches the power generator could be included in the timing controller. This is a known arrangement that could, e.g., simplify manufacture. One of ordinary skill in the art could have included it with predictable results.
Regarding (B):
Jang discloses:
detecting whether an image signal is abnormal (e.g., paragraph 8).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Hong in view of Lee a first register, wherein at least part of information stored in the first register is set by the timing controller as a first information when the image signal is abnormal, and one of the plurality of feedback sub-signals corresponding to the image signal comprises the first information, as suggested by Jang.
The rationale is as follows:
Hong, Lee, and Jang are directed to the same field of art.
Hong already tests for abnormalities and stores the result in a register when a signal is abnormal. Jang teaches that an image signal should be tested for abnormalities. Testing this signal could improve performance. This is a known improvement that one of ordinary skill in the art could have included with predictable results.
Regarding claim 4:
Hong, etc., discloses:
a system chip electrically connected to the timing controller, and configured to provide the image signal and an original power signal to the timing controller, wherein the original power signal is configured to supply power to the timing controller (Hong paragraph 36, where the timing controller is part of the drive circuit as per, e.g., Fig. 3).
Regarding claim 5:
Hong, etc., discloses:
wherein the system chip is configured to generate an image abnormality signal in response to the first information (this is displayed as per Hong paragraph 126).
Regarding claim 6:
Hong, etc., discloses:
a power manager electrically connected to the system chip and the timing controller (Hong Fig. 3: 122), wherein the power manager is configured to acquire the original power signal from the system chip (this is Vin), and is further configured to generate a first power signal transmitted to the timing controller in response to the original power signal, and the power signal comprises the first power signal (if as follows from Lee the power manager is in the timing controller, the power manager still generates the first power signal, and it is transmitted to the timing controller because it is a part of it, and the test then would be done inside the power signal).
Regarding claim 7:
Hong, etc., discloses:
a gate driver electrically connected to the power manager and a plurality of sub- pixels of the display panel (Hong Fig. 1: 130), and configured to generate gate signals that act on the plurality of sub-pixels in response to a second power signal (Hong Fig. 1: V1), wherein the power manager is further configured to generate the second power signal transmitted to the gate driver in response to the original power signal, and the power signal comprises the second power signal (as per Hong Fig. 3 the power generator generates both the first signal V2 and the second V1 in response to Vin).
Regarding claim 8:
Hong, etc., discloses:
the system chip is configured to generate a power abnormality signal in response to the second information (Lee taught having this be part of the timing generator).
Regarding claim 9:
Hong, etc., discloses:
a source driver electrically connected to the power manager and the plurality of sub-pixels of the display panel, and configured to generate data signals that act on the plurality of sub-pixels in response to the first power signal (the data driver of Hong Fig. 1: 100, which receives V2 as seen in the figure).
Regarding claim 11:
All elements positively recited have already been identified with respect to earlier rejections. No further elaboration is necessary.
Regarding claim 15:
This is a claim to the method performed by the display device of claim 1. It is met when the display device operates. No further elaboration is necessary.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee and Jang, and further in view of Arima (US 2017/0186349)
Regarding claim 10:
Hong, etc., discloses a display device as discussed above.
Hong, etc., does not disclose:
“wherein the second information comprises a first sub-information corresponding to an abnornality of the first power signal, a second sub-information corresponding to an abnormality of the second power signal, and a third sub-information corresponding to a situation that both the first power signal and the second power signal are abnormal.”
Arima discloses:
wherein the second information comprises a first sub-information corresponding to an abnornality of the first power signal, a second sub-information corresponding to an abnormality of the second power signal, and a third sub-information corresponding to a situation that both the first power signal and the second power signal are abnormal (paragraph 96: there’s a separate bit for each signal; note that the third sub-information will occur if both bits are set to abnormal).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Hong, etc., the elements taught by Arima.
The rationale is as follows:
Hong, Lee Jang, and Arima are directed to the same field of art.
Hong already detects these abnormalities; Arima just discloses a way they can be communicated to the processor (paragraph 99). This is a known improvement one of ordinary skill in the art could have included with predictable results.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee and Jang, and further in view of Wang (US 2019/0266931)
Regarding claim 12:
Hong, etc., does not disclose:
“wherein the timing controller comprises: pins, wherein potentials of the pins are outside a preset potential range when the power signal is abnormal; and wherein the timing controller is configured to set the at least part of the information stored in the second register as the second information when the potentials of the pins are outside the preset potential range.”
Wang discloses:
pins, wherein potentials of the pins are outside a preset potential range when the power signal is abnormal (paragraph 29).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Hong in view of Jang wherein the timing controller comprises: pins, wherein potentials of the pins are outside a preset potential range when the power signal is abnormal; and wherein the timing controller is configured to set the at least part of the information stored in the second register as the second information when the potentials of the pins are outside the preset potential range, as suggested by Wang.
The rationale is as follows:
Hong, Lee, Jang, and Wang are directed to the same field of art.
Neither Hong, Lee, or Jang discuss in detail where the voltage is measured. Wang shows that this is done by measuring the potential of output or input pins. One of ordinary skill in the art could have included this with predictable results.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee Jang, and further in view of Huitema et al. (US 2021/0272510)
Regarding claim 13:
Hong, etc., discloses:
wherein the power manager and the timing controller are integrated on a circuit board (Hong paragraph 58).
Hong, etc., does not disclose:
“the system chip and the first circuit board are electrically connected through a first chip-on-film.”
Huitema discloses:
the system chip and the first circuit board are electrically connected through a first chip-on-film (paragraph 28).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Hong , etc., the elements taught by Huitema.
The rationale is as follows:
Hong, Lee, Jang, and Huitema are directed to the same field of art.
Huitema discloses a known way that the circuit board and host system can be connected. One of ordinary skill in the art could have included this with predictable results.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong in view of Lee and Jang, and further in view of Hwang et al. (US 2016/0189581)
Regarding claim 14:
Hong, etc., discloses a display system as discussed above.
Hong, etc., does not disclose:
“a plurality of display devices according to claim l; and a central control device configured for receiving the feedback signal output by each of the plurality of display devices.”
Hwang discloses:
a plurality of display devices; and a central control device configured for receiving the feedback signal output by each of the plurality of display devices (paragraph 14).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include in Hong, etc., the elements taught by Hwang.
The rationale is as follows:
Hong, etc., and Hwng are directed to the same field of art.
Hwang discloses this can simplify signal lines and wiring (paragraph 14). This is a known improvement that one of ordinary skill in the art could have included with predictable results.
Response to Arguments
Applicant's arguments filed 28 May 2026 have been fully considered but they are not persuasive.
Applicant first argues (page 2) that Hong does not determine abnormalities of a power signal. Applicant points to where Hong detects temperature, voltage, current, and a dummy gate signal. But if it detects voltage and current, aren’t those abnormalities of a power signal?
Perhaps the argument here is that this is not a power signal supplied to the timing controller. It is true that in Hong these signals come from the power generator rather than the timing controller. For this reason Lee has been relied upon to show that this power generator could be included in the timing controller.
Really Hong works much the same way as applicant. Applicant has a power signal that is input to the power controller, which uses it to create a second power signal (as per, e.g., applicant’s own claim 4), which is the one tested. Since it derives from the original power signal perhaps it can be argued that testing the second power signal is looking for abnormalities in this original signal. This is the same process Hong does – it uses the original signal to generate power signals for the data and gate drivers and tests those.
Applicant’s second argument (still page 2) is that Hong doesn’t set a register value when the image signal is abnormal. Well, because all of Hong’s signals are used to control the image, arguably every one of them is an image signal. Nor is applicant’s own specification really all that clear on what is being tested here or what exactly this image signal is. But in order to resolve applicant’s arguments, Jang has been relied upon. Jang explicitly calls the test signal an “image signal.”
Applicant’s third argument (still page 2) is that Hong doesn’t set a register value for a power signal abnormality. There’s only two things involved in a power signal: voltage and current. Hong tests them both and puts them in the register.
Applicant’s fourth argument (still page 2) is that Hong doesn’t disclose that a feedback signal has both image signal abnormalities and power signal abnormalities. This argument is moot in view of the newly relied upon Jang.
Therefore applicant’s argument are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER R LAMB/ Primary Examiner, Art Unit 2622
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