CTNF 19/237,059 CTNF 87861 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 Claims 1, 3-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,367,825. Although the claims at issue are not identical, they are not patentably distinct from each other. Application 19/237,059 Patent No. 12,367,825 1. A display panel, comprising a pixel driving circuit, wherein the pixel driving circuit comprises: a drive transistor, a first electrode of the drive transistor being connected to a first power line; a first capacitor, a first electrode of the first capacitor being connected to a gate of the drive transistor; a second capacitor, a first electrode of the second capacitor being connected to a second electrode of the first capacitor, and a second electrode of the second capacitor being configured to receive a power supply voltage signal; wherein the display panel further comprises: a substrate; a first conductive layer on one side of the substrate, comprising a first conductive portion configured to form the gate of the drive transistor and the first electrode of the first capacitor; a second conductive layer on one side of the first conductive layer away from the substrate, comprising a second conductive portion, wherein an orthographic projection of the second conductive portion on the substrate at least partially overlaps with an orthographic projection of the first conductive portion on the substrate; and the second conductive portion is configured to form the second electrode of the first capacitor and the first electrode of the second capacitor; and a third conductive layer on one side of the second conductive layer away from the substrate, comprising a third conductive portion, wherein an orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate; and the third conductive portion is configured to form the second electrode of the second capacitor. 1. A display panel, comprising a pixel driving circuit, wherein the pixel driving circuit comprises: a drive transistor, a first electrode of the drive transistor being connected to a first power line; a first capacitor, a first electrode of the first capacitor being connected to a gate of the drive transistor; a second capacitor, a first electrode of the second capacitor being connected to a second electrode of the first capacitor; a first transistor, a first electrode of the first transistor being connected to a data line, and a second electrode of the first transistor being connected to a second electrode of the second capacitor; and a fifth transistor, a first electrode of the fifth transistor being connected to the second electrode of the first capacitor and a second electrode of the fifth transistor being connected to a stabilized power supply terminal; wherein the display panel further comprises: a substrate; a first conductive layer on one side of the substrate, comprising a first conductive portion configured to form the gate of the drive transistor and the first electrode of the first capacitor; a second conductive layer on one side of the first conductive layer away from the substrate, comprising a second conductive portion, wherein an orthographic projection of the second conductive portion on the substrate at least partially overlaps with an orthographic projection of the first conductive portion on the substrate; and the second conductive portion is configured to form the second electrode of the first capacitor and the first electrode of the second capacitor; and a third conductive layer on one side of the second conductive layer away from the substrate, comprising a third conductive portion, wherein an orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate, and the orthographic projection of the third conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate; and the third conductive portion is configured to form the second electrode of the second capacitor. Application 19/237,059 Claim 3 Claim 4 Claim 5 Claim 6 Claim 7 Claim 8 Claim 9 Claim 10 Claim 11 Patent No. 12,367,825 Claim 2 Claim 3 Claim 1 Claim 1 Claim 6 Claim 7 Claim 8 Claim 9 Claim 10 Application 19/237,059 Claim 12 Claim 13 Claim 14 Claim 15 Claim 16 Claim 17 Claim 18 Claim 19 Claim 20 Patent No. 12,367,825 Claim 11 Claim 12 Claim 13 Claim 14 Claim 15 Claim 16 Claim 17 Claim 18 Claim 19 Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J KOHLMAN whose telephone number is (571)270-5503. The examiner can normally be reached 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, NITIN PATEL can be reached at (571) 272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER J KOHLMAN/Primary Examiner, Art Unit 2628 Application/Control Number: 19/237,059 Page 2 Art Unit: 2628 Application/Control Number: 19/237,059 Page 3 Art Unit: 2628 Application/Control Number: 19/237,059 Page 4 Art Unit: 2628 Application/Control Number: 19/237,059 Page 5 Art Unit: 2628 Application/Control Number: 19/237,059 Page 6 Art Unit: 2628 Application/Control Number: 19/237,059 Page 7 Art Unit: 2628 Application/Control Number: 19/237,059 Page 8 Art Unit: 2628 Application/Control Number: 19/237,059 Page 9 Art Unit: 2628
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