DETAILED ACTION
Status of Application
Claims 1-20 are pending in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 10, 12-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaue (US 20210399063 A1), further in view of Lin et al. (US 20210193049 A1).
Regarding claim 1, Yamaue teaches A display apparatus comprising: a gate driving circuit; (Fig. 2. Gate driving circuit 50L and 50R. Para 22-23)
and a pixel circuit including a first transistor, a second transistor, a driving transistor, a first transistor-1, and an emission element, (Fig. 3: a first transistor T5, a second transistor T6, a driving transistor T1, a first transistor-1 T4 to different from the first (oxide) transistor, and an emission element OLED. Para 34)
wherein: the driving transistor includes a gate electrode connected to a first node, a source electrode, and a drain electrode, (Fig. 3: driving transistor T1. With a gate electrode connected to a first node, a source electrode, and a drain electrode. Para 34)
the first transistor and the second transistor are connected to the first node, (Fig 3: T6 and T5 are the first and second transistor connected to the first node)
the first transistor-1 is connected to a second node, the second node connected to any one of the source electrode and the drain electrode of the driving transistor, (fig. 3: T4 connected to the second node connected to any one of the source electrode and the drain electrode of the driving transistor T1)
a first region of the gate driving circuit is disposed on a first side of an active area including the pixel circuit, a second region of the gate driving circuit is disposed on a second side of the active area, each of the first region and the second region of the gate driving circuit includes an emission signal stage and at least one scan signal stage connected to the pixel circuit, and the at least one scan signal stage disposed between the emission signal stage and the active area. (Par 22-23. Fig. 2: 60L and 60R are the emission signal stage, and 50L and 50R are the gate driving circuit, and display region 5 with pixels 11 are the active area, and gate driving circuit is between the emission driver and the active area as shown in Fig. 2.)
However Yamamue does not teach a first transistor is a oxide transistor, a second transistor is a oxide transistor, the driving transistor and the first transistor-1 include a low temperature polycrystalline silicon.
However teach transistor can be oxide transistor and transistor formed from low temperature polycrystalline silicon. (Para 34, 47)
Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Yamamue with Lin to teach a first transistor is a oxide transistor, a second transistor is a oxide transistor, the driving transistor and the first transistor-1 include a low temperature polycrystalline silicon in order to produce the predictable result of image display with the transistor configuration as taught by Lin.
Regarding claim 2, Yamamue and Lin already teach The display apparatus according to claim 1,
and Yamamue further teaches wherein the pixel circuit further comprises: a first capacitor connected between the first node and a fourth node. (Fig. 3: C1 between the first node and a fourth node next to T3)
Regarding claim 3, Yamamue and Lin already teach the display apparatus according to claim 2,
And Yamamue further teaches wherein the pixel circuit further comprises: a second capacitor connected between the first node and a first voltage supply line, (Fig. 3: C1 is also the second capacitor. C1 between ELVDD and the first node)
the first voltage supply line connected to another one of the source electrode and the drain electrode of the driving transistor. (Fig. 3: ELVDD connected to another one of the source electrode and the drain electrode of the driving transistor T1 through T3)
Regarding claim 4, Yamamue and Lin already teach the display apparatus according to claim 2,
And Yamamue further teaches wherein the pixel circuit further comprises: a third oxide transistor connected between a data line and the fourth node; (Fig. 3: T2 between the data line D(m) and the fourth node next to T3. Oxide transistor is taught by Lin as shown in rejection for claim 1.)
and a fourth oxide transistor connected between a reset voltage supply line and a fifth node between the first transistor and the emission element. (Fig. 3: T5 is also the fourth oxide transistor connected between a reset voltage suppl line ELVDD through C1, and a fifth node between the first transistor and OLED through T4. Oxide transistor is taught by Lin as shown in rejection for claim 1.)
Regarding claim 5, Yamamue and Lin already teach the display apparatus according to claim 4,
And Yamamue further teaches wherein the at least one scan signal stage includes a first scan signal stage, wherein the first scan signal stage is configured to output a first scan signal to a gate electrode of the first oxide transistor and a gate electrode of the third oxide transistor through a first scan line, (Fig. 3: G(p) connected to T5 and T2. Para 34)
and wherein a first scan signal of a pre-previous pixel row is applied to a gate electrode of the second oxide transistor through a second scan line. (Fig. 3: G(p-1) connected to T6.)
Regarding claim 6, Yamamue and Lin already teach the display apparatus according to claim 4,
And Yamamue further teaches wherein the emission signal stage is configured to output an emission signal to a gate electrode of the first transistor, and wherein the first transistor is controlled by the emission signal and is configured to connect the second node and the emission element. (Fig. 3: EM(p) to T4, and T4 connected to the OLED. Para 34)
Regarding claim 10, Yamamue and Lin already teach the display apparatus according to claim 4,
And Yamamue further teaches wherein the pixel circuit further comprises: a second transistor controlled by a second scan signal of a third scan line and configured to connect the fourth node to a reference voltage supply line, and wherein the at least one scan signal stage includes a second scan signal stage outputting the second scan signal. (Fig. 3: T2 is the second transistor controlled a third scan line G(p). T2 connected to ELVDD through fourth node. Fig. 2 shows scan lines connected to different stage. Para 24.)
Regarding claim 12, Yamamue and Lin already teach the display apparatus according to claim 1,
And Yamamue further teaches wherein the first oxide transistor is controlled by a first scan signal of a first scan line and is configured to connect the first node and the second node, (Fig. 3: T5 connected to G(p), connected to first node and second node.)
and wherein the second oxide transistor is controlled by a first scan signal supplied to a first scan line of a pre-previous pixel row and is configured to connect the first node to an initialization voltage supply line. (Fig. 3: T6 connected to G(p-1), and connected to Vini to gate of T1).
Regarding claim 13, Yamamue teach a display apparatus comprising: a gate driving circuit; (Fig. 2. Gate driving circuit 50L and 50R. Para 22-23)
and a pixel circuit including a first transistor, a second transistor, a driving transistor, a first-1 transistor, and an emission element, (Fig. 3: a first transistor T6, a second transistor T5, a driving transistor T1, a first transistor-1 T4 to different from the first (oxide) transistor, and an emission element OLED. Para 34)
wherein: the driving transistor includes a gate electrode connected to a first node, a source electrode, and a drain electrode, (Fig. 3: driving transistor T1. With a gate electrode connected to a first node, a source electrode, and a drain electrode. Para 34)
the first transistor and the second transistor are connected to the first node, (Fig 3: T6 and T5 are the first and second transistor connected to the first node)
the first transistor-1 is connected to a second node, the second node connected to any one of the source electrode and the drain electrode of the driving transistor, (fig. 3: T4 connected to the second node connected to any one of the source electrode and the drain electrode of the driving transistor T1)
a first region of the gate driving circuit is disposed on a first side of an active area including the pixel circuit, a second region of the gate driving circuit is disposed on a second side of the active area, the first region of the gate driving circuit includes a first scan signal stage connected to the pixel circuit, the second region of the gate driving circuit includes a second scan signal stage and an emission signal stage connected to the pixel circuit, and the second scan signal stage disposed between the active area and the emission signal stage. (Par 22-23. Fig. 2: 60L and 60R are the emission signal stage, and 50L and 50R are the gate driving circuit, and display region 5 with pixels 11 are the active area, and gate driving circuit is between the emission driver and the active area as shown in Fig. 2.)
However Yamamue does not teach a first transistor is a oxide transistor, a second transistor is a oxide transistor, the driving transistor and the first transistor-1 include a low temperature polycrystalline silicon.
However teach transistor can be oxide transistor and transistor formed from low temperature polycrystalline silicon. (Para 34, 47)
Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Yamamue with Lin to teach a first transistor is a oxide transistor, a second transistor is a oxide transistor, the driving transistor and the first transistor-1 include a low temperature polycrystalline silicon in order to produce the predictable result of image display with the transistor configuration as taught by Lin.
Regarding claim 14, refer to rejection for claim 2.
Regarding claim 15, refer to rejection for claim 3.
Regarding claim 16, Yamamue and Lin already teach the display apparatus according to claim 15,
And Yamamue further teaches wherein the pixel circuit further comprises: a third oxide transistor connected between a data line and the fourth node; (Fig. 3: T2 between the data line D(m) and the fourth node next to T3. Oxide transistor is taught by Lin as shown in rejection for claim 1.)
a fourth oxide transistor connected between a reset voltage supply line and a fifth node between the first transistor and the emission element; (Fig. 3: T5 is also the fourth oxide transistor connected between a reset voltage suppl line ELVDD through C1, and a fifth node between the first transistor and OLED through T4. Oxide transistor is taught by Lin as shown in rejection for claim 1.)
and a second transistor connected between the fourth node and a reference voltage supply line. (Fig. 3: T5 is the second transistor connected between the fourth node and a reference voltage supply line ELVDD through C1, T1 and T3).
Regarding claim 17, Yamamue and Lin already teach the display apparatus according to claim 16,
And Yamamue further teaches wherein the first scan signal stage is configured to output a first scan signal to a gate electrode of the first oxide transistor and a gate electrode of the third oxide transistor through a first scan line, (Fig. 3: G(p) connected to T5 and T2. Para 34)
wherein a first scan signal of a pre-previous pixel row is applied to a gate electrode of the second oxide transistor through a second scan line, (Fig. 3: G(p-1) connected to T6.)
and wherein the second scan signal stage is configured to output a second scan signal to a gate electrode of the second transistor through a third scan line. (Fig. 3: T5 is the second transistor controlled a third scan line G(p). Fig. 2 shows scan lines connected to different stage. Please note that there are scan driver on both sides with scan lines connected to the transistor from both sides. the Para 24.)
Regarding claim 20, Yamamue and Lin already teach the display apparatus according to claim 13,
And Yamamue further teaches wherein the first oxide transistor is controlled by a first scan signal of a first scan line and is configured to connect the first node and the second node, (Fig. 3: T5 connected to G(p), connected to first node and second node.)
and wherein the second oxide transistor is controlled by a first scan signal supplied to a first scan line of a pre-previous pixel row and is configured to connect the first node to an initialization voltage supply line. (Fig. 3: T6 connected to G(p-1), and connected to Vini to gate of T1).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaue (US 20210399063 A1), in view of Lin et al. (US 20210193049 A1), further in view of Lee et al. (US 20200126478 A1).
Regarding claim 11, Yamamue and Lin already teach the display apparatus according to claim 10,
However Yamamue and Lin do not teach wherein at least one of the driving transistor, the first transistor, and the second transistor has a first conductivity type, and wherein least one of the first to fourth oxide transistors has a second conductivity type.
However Lee teaches pixel circuit may be formed of nfet and pfet. (Para 37. In the 2T1C pixel circuit as illustrated in FIG. 1A, the switch transistor T0 is an n-type transistor, and the driving transistor N0 is a p-type transistor.)
Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Yamamue and Lin with Lee to teach wherein at least one of the driving transistor, the first transistor, and the second transistor has a first conductivity type, and wherein least one of the first to fourth oxide transistors has a second conductivity type in order to produce the predictable result of image display with n-type and p-type transistors as taught by Lee.
Allowable Subject Matter
Claims 7-9 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/HANG LIN/Primary Examiner, Art Unit 2626
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