DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1, 8-9, 15-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6, 11, 15-16 of U.S. Patent No.12,373,099. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following analysis:
Instant application 19/237,836
U.S. Patent 12,373,099
1. A memory system, comprising: a memory chip including: a memory cell array including a first data area and a second data area; a first interface circuit configured to receive a program command for storing data in the memory cell array at an address; a first control circuit configured to control a program operation of data to the first data area based on the program command and the address; a control chip including: a second interface circuit configured to receive a write command including data and an address from a host; and a second control circuit configured to issue the program command to the memory chip based on the write command, wherein when a first command is received by the control chip from the host, the second control circuit is configured to read data written by a first writing method corresponding to a first number of cell bits from the first data area, and then rewrite the just read data to the second data area by a second writing method corresponding to a second number of cell bits less that is less than the first number of cell bits, and when a read command corresponding to the read data associated with the first command is received from the host after the first command, the second control circuit is configured to read the rewritten data from the second data area and transfer the data to the host.
1. A memory system, comprising: a memory array; and a controller configured to: when a write command is received is received from a host device, cause first data to be written into the memory array by a first method which provides a first read transfer time to the host device when the first data is read, when a first command is received, cause the first data written by the first method to be read from the memory array, then rewritten into the memory array by a second method which provides a second read transfer time when the first data is read, the second read transfer time being less than the first read transfer time, and when a read command is received after the first command, cause the first data written by the second method to be read from the memory array and transferred to the host device.
4. The memory system according to claim 1, wherein the memory array has a different memory area for each of the first and second methods.
8. The memory system according to claim 1, wherein the memory chip stores a lookup table, and the second control circuit is configured to change the lookup table in response to the rewrite after the first command is received, the lookup table being changed to reflect the movement of data from the first data area to the second data area by the rewrite.
6. The memory system according to claim 1, wherein the controller is configured to maintain a logical-to-physical address conversion table for converting a logical address of data designated by the host device into a physical address of the memory array and to update the logical-to-physical address conversion table upon rewriting the first data using the second method in response to the first command.
9. A memory control chip, comprising: a host interface circuit configured to receive a write command including data and an address from a host; and a control circuit configured to issue a program command to a memory chip based on the write command, wherein when a first command is received by the host interface circuit from the host, the control circuit is configured to read data written by a first writing method corresponding to a first number of cell bits from a first data area in a memory chip, and then rewrite the just read data to a second data area in the memory chip by a second writing method corresponding to a second number of cell bits less that is less than the first number of cell bits, and when a read command corresponding to the read data associated with the first command is received by the host interface circuit from the host after the first command, the control circuit is configured to read the rewritten data from the second data area and transfer the data via the host interface circuit to the host.
11. A memory controller, comprising: a host interface configured to communicate with a host device and receive commands from the host device; a memory interface configured to communicate with a memory array; and a processor configured to: when a write command is received is received from the host device, cause first data to be written into the memory array by a first method which provides a first read transfer time to the host device when the first data is read, when a first command is received, cause the first data written by the first method to be read from the memory array, then rewritten into the memory array by a second method which provides a second read transfer time when the first data is read, the second read transfer time being less than the first read transfer time, and when a read command is received after the first command, cause the first data written by the second method to be read from the memory array and transferred to the host device.
15. The memory control chip according to claim 9, wherein the memory chip stores a lookup table, and the control circuit is configured to change the lookup table in response to the rewrite after the first command is received, the lookup table being changed to reflect the movement of data from the first data area to the second data area by the rewrite.
15. The memory controller according to claim 14, wherein the processor is further configured to update the logical-to-physical address conversion table to associate the logical address of the first data with the initial location from the secondary logical-to-physical address conversion table upon receiving either a second command from the host device via the host interface or a power down notice.
16. A memory control method, comprising: receiving a write command including data and an address from a host; and issue a program command to a memory chip based on the write command, wherein when a first command is received from the host, data written by a first writing method corresponding to a first number of cell bits is read from a first data area in a memory chip, and then the just read data is rewritten to a second data area in the memory chip by a second writing method corresponding to a second number of cell bits less that is less than the first number of cell bits, and when a read command corresponding to the read data associated with the first command is received from the host after the first command, the rewritten data is read from the second data area and then transferred to the host.
18. A memory control method, comprising: writing first data into a memory array using a first writing method which provides a first read transfer time to the host device when the first data is read; upon receiving a first command from a host device, reading the first data designated by the first command from the memory array and then rewriting the data to the memory array using a second writing method which provides a second read transfer time to the host device when the first data is read, the second read transfer time being less than the first read transfer time; and upon receiving a read command from the host device after the first command, causing the first data written by the second writing method to be read from the memory array and transferred to the host device.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,373,099 in view of JEDEC Standard Version 1.01, November 2023.
Patent 12,373,099 does not disclose “The memory system according to claim 1, wherein the first interface circuit is a Universal Flash Storage (UFS) host controller interface (UFSHCI), Version 2.1, March 2016.”
However, UFS standard suggests using the UFS host interface, and device interface for fast data transmission ( Section 1, Section 4). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the JEDEC standard into the Patent 12,373,099 to obtain the claimed limitation above. The motivation for doing so is to apply a known technique in to a system/method of Patent 12,373,099 to yield predictable result.
Claims 1, 9, 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 11, and 18 of U.S. Patent No. 11,809,708 in view of Lee et al (U.S. 10,515,693).
Regarding claim 1:
Claims 1 and 4 of Patent 11,809,708 discloses “A memory system, comprising: a memory array having a plurality of memory cells configured to store two or more bits of data in each of the memory cells; and a memory controller configured to cause data to be written into of the plurality of memory cells using writing methods for different number of bits of data and cause the data written into the plurality of memory cells to be read, wherein when a first command is received from a host, the memory controller is configured to cause data indicated by the first command to be read from the plurality of memory cells, and then cause the read data to be rewritten into the plurality of memory cells using a writing method for a fewer number of bits per memory cell than the writing method used to write the data to the plurality of memory cells before the reading of the data, and when a read command corresponding to the data indicated by the first command is received from the host after the first command, the memory controller is configured to read the rewritten data from the plurality of memory cells, and then transfer the data to the host; wherein the memory array has a memory area for each of the different writing methods”. However, Patent 11,809,708, does not disclose first interface circuit, a first control circuit, a control chip including a second interface. In an analogous art of storage management, Lee discloses a data storage apparatus (Fig. 1) comprises a controller which further includes memory interface, a host interface. The controller is configured to receive read/write commands from host, and issues commands or performs read/write operations to memory devices (5:5-15, 6:1-15). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Lee into the Patent 11,809,708 to obtain the claimed limitation above. The motivation for doing so is to apply a known device/technique into the system ready for improvement of Patent 11,809,708 to yield predictable result.
Claims 9 and 16 recites similar limitations correspond to claims 11 and 18 of Patent 11,809,708, and are rejected under same rationale cited in claim 1.
Allowable Subject Matter
Claims 1-20 are allowed if overcome the double patenting rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bi et al (U.S. 2023/0305738) discloses a technique to write data in either SLC or MLC cells of a non-volatile memory device.
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/KHOA D DOAN/Primary Examiner, Art Unit 2133
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