DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation “writing to the allocated memory resource of the memory pool”. The “allocated memory resource”, in the claim, was not migrated to the memory pool. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 10, 15, 18-19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Van Doren et al (U.S. 2004/0066758), Shalf et al (U.S. 10,102,179), and in view of Michaud et al (U.S. 10,459,852).
Regarding claim 1:
A system comprising: a memory pool configured with memory resources and service read and write requests to the memory resources; Van Doren discloses a computer system (Fig. 2) comprises a memory pool 302a (Fig .4).
one or more multi-CPU-socket chassis forming a high-performance computing (HPC) system, including a first multi-CPU-socket chassis, wherein the first multi-CPU-socket chassis has a plurality of sockets, wherein each socket of the first multi-CPU-socket chassis is operatively coupled to the memory pool, wherein the first multi-CPU-socket chassis comprises: a plurality of processing units connected to the plurality of sockets, including a first processing unit; and a plurality of local memories, including a first local memory, wherein the first local memory has instructions stored thereon, wherein execution of the instructions causes the plurality of processing units to: Van Doren, Figs. 2-3, multiprocessor node comprises a plurality of sockets (e.g. S0-S7). Fig. 4 shows a configuration of a socket (S0), which comprises CPU 404 (processing unit), local memories 406, and processor caches (¶0043). Van Doren further discloses the idea of storing data in cache ( allocate a memory resource in a local memory), ¶0009.
However, Van Doren does not disclose, but in an analogous art of multi-core memory system, Shalf discloses allocate a memory resource, from the first local memory, for a computing process, wherein the allocated memory resource is accessible by each of the plurality of processing units of the first multi-CPU-socket chassis; Shalf further discloses each of processor cores 110 (or at least one or more of the processor cores 110) is configured to be able to address any of local memories 114 (or at least one or more of the local memories 114 besides its own). In particular, each processor core 110 (or at least one or more of the processor cores 110) contains a local memory 114 configured to be visible in a global memory address space of the multiple-core processor 100 so that it is visible to all other processor cores 110 (or at least one or more of the other processor cores 110) of the multiple-core processor 100 (3:15-25, 3:55-65). It has been interpreted Shalf suggests the idea of multiple cores can access a shared resource, or an allocated resource of other core memories. wherein the [migrated allocated] memory resource in the memory pool is directly accessible by the plurality of processing units without an access request being presented to the first processing unit. Each of the cores is able to access/write data in main memory without requesting other cores since the data is in main memory. The data is not in any local caches/memories, or in known coherency states such as MESI, MOESI (5:35-45). Van Doren also teaches the idea of any processor can access data that has been written-back to main memory (¶0008-¶0010).
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Shalf into the teaching of Van Doren to consider allocating a memory resource from a local memory of a first processor core of a plurality processor cores for a computing process, and allowing access to the allocated memory resource to other cores. The motivation for doing so is to apply a known technique, taught by Shalf, into the system ready for improvement of Van Doren to yield predictable results, which make the multi-cores system more efficient and effective (Shalf, 5:35-55).
However, the combination of Van Doren and Shalf does not teach migrate the allocated memory resource to the memory pool based on a number of tracked accesses to the allocated memory resource by the plurality of processing units,
In an analogous art of cache management, Michaud discloses an idea to track how frequently cached data is accessed to decide when to evict the cached data to main memory (11:5-40). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Michaud into the system ,ready for improvement, of Van Doren and Shalf, hereinafter Van Doren, to have migrate an allocated resource in a local memory or a local cache to a memory pool or a main memory based on access frequency of the allocated memory resource. The motivation for doing so is to apply a known technique into a known system to yield predictable result.
Thus, together the combination of Van Doren discloses wherein the migrated allocated memory resource in the memory pool is directly accessible by the plurality of processing units without an access request being presented to the first processing unit. Each of the cores is able to access/write data in main memory without requesting other cores since the data is in main memory. The data is not in any local caches/memories, or in known coherency states such as MESI, MOESI (5:35-45).
Regarding claim 19:
Claim 19 recites the method similar to the operating steps of claim 1, and is rejected under same rationale cited in claim 1.
Regarding claim 2:
The system of claim 1, wherein the one or more multi-CPU-socket chassis include a second multi-CPU-socket chassis having a second plurality of sockets, wherein each socket of the second multi-CPU-socket chassis is operatively coupled to the memory pool, wherein each of the second plurality of sockets is connected to a second plurality of local memories, and wherein each of the second plurality of sockets is connected to the memory pool. Van Doren, Figs. 2-4, multiple socket S0-S7, each socket comprises CPU, local cache, and connects to memory subsystem via interconnect fabric. The processors and memory subsystems of the system communicate with each other by exchanging command packets that are carried by the SMP system within a plurality of virtual channels (¶0025).
Regarding claim 3:
The system of claim 1, wherein each of the one or more multi-CPU-socket chassis has a respective plurality of processing units connected to a respective plurality of sockets, wherein each of the respective plurality of sockets of each of the one or more multi-CPU- socket chassis is connected to a respective plurality of local memories, and wherein each of the respective plurality of sockets of each of the multi-CPU-socket chassis is connected to the memory pool. Van Doren, Figs. 2-4, multiple socket S0-S7, each socket comprises CPU, local cache, and connects to memory subsystem via interconnect fabric. The processors and memory subsystems of the system communicate with each other by exchanging command packets that are carried by the SMP system within a plurality of virtual channels (¶0025). Shalf, Fig. 1, each processor includes a plurality of cores.
Regarding claim 10:
The system of claim 1, wherein each of the plurality of sockets receives a microprocessor having a plurality of cores or chiplets as a subset of the plurality of processing units. Shalf suggests that the processor can be a multi-core processor, or a many-core processor, which would be obvious to have a plurality of cores as a subset (Shalf, 2:5-15).
Regarding claim 15:
The system of claim 3, wherein the respective plurality of sockets of each of the one or more multi-CPU-socket chassis includes 2 to 64 sockets. Van Doren, Fig. 4, a plurality of socket S0-S7.
Regarding claim 18:
The system of claim 1, wherein the allocation of the memory resource occurs on the memory pool, wherein the allocated memory resource on the memory pool is directly accessible by the plurality of processing units without an access request being presented to the first processing unit. Shalf discloses each processor core 110 (or at least one or more of the processor cores 110) contains a local memory 114 configured to be visible in a global memory address space of the multiple-core processor 100 so that it is visible to all other processor cores 110 (or at least one or more of the other processor cores 110) of the multiple-core processor 100 (3:15-25, 3:55-65). Shalf also discloses the main memory maybe external or internal to the multi-core processor (3:45-55) as a local memory. Van Doren discloses each CPU 404 of the SMP system 300 may access portions of memory stored at the two memory subsystems 302 coupled to its socket, i.e., a "local" memory access, or at the memory subsystems coupled to any other socket of the SMP system 300, i.e., a "remote" memory access (¶0061). Thus, the memory resource on the memory pool is accessible by other processors.
Regarding claim 21:
A method comprising:
providing a memory pool configured with memory resources and service read and write requests to the memory resources, wherein the memory pool is accessible by a plurality of multi- CPU-socket chassis, Shalf, Fig. 1, main memory 130 is configured to service read/write from processor cores 110, which reside together on one or more printed circuit boards (3:45-55, and 3:60-65 4:1-5, 5:45-50).
allocating a memory resource from the first local memory for a computing process; Each of the processor cores 110 includes a local memory 114, and a local cache 118, where are automatically-controlled to store data, which is effectively allocate memory resource to store data(2:60-65, 3:1-35). Shalf further discloses each of processor cores 110 (or at least one or more of the processor cores 110) is configured to be able to address any of local memories 114 (or at least one or more of the local memories 114 besides its own). In particular, each processor core 110 (or at least one or more of the processor cores 110) contains a local memory 114 configured to be visible in a global memory address space of the multiple-core processor 100 so that it is visible to all other processor cores 110 (or at least one or more of the other processor cores 110) of the multiple-core processor 100 (3:55-65).
and writing to the allocated memory resource of the memory pool based on the computing process, wherein the allocated memory resource in the memory pool is directly and natively accessible by the plurality of processing units without an access request being presented to one of the processing units. Each of the cores is able to access/write data in main memory without requesting other cores since the data is in main memory. The data is not in any local caches/memories, or in known coherency states such as MESI, MOESI (5:35-45).
The examiner notes that the previous two limitations, as filed, are not directly correspond to each other, because the allocation in a local memory can occur independent from writing data to memory pool.
Shalf does not teach a plurality of multi-CPU-socket chassis including a first multi-CPU-socket chassis comprising (i) a plurality of processing units connected to a plurality of sockets, including a first processing unit and (ii) a plurality of local memories, including a first local memory; In an analogous art of memory management, Van Doren discloses a symmetrical multiprocessor system with a shared memory, Fig. 2, multiprocessor node comprises a plurality of sockets (e.g. S0-S7). Fig. 4 shows a configuration of a socket (S0), which comprises CPU 404, local memories 406, and processor caches (¶0043).
Claims 4-8, 12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Van Doren et al (U.S. 2004/0066758), Shalf et al (U.S. 10,102,179), and in view of Michaud et al (U.S. 10,459,852), and further in view of Norman et al (U.S. 2021/0263673).
Regarding claim 4:
The system of claim 3, wherein each of the respective plurality of sockets is connected to the memory pool via a Compute Express Link (CXL). The combination of Van Doren does not teach the claimed limitation above. However, in an analogous art of memory management, Norman, Fig. 7, suggest a shared memory 110 connects to plurality of CPU 110-1 to 110-8 using CXL channels (¶0071). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Norman into the combination of Van Doren to obtain the claimed limitation above. The motivation for doing so is to apply a known technique, taught by Norman, into the system ready for improvement of Van Doren to yield predictable results.
Regarding claim 5:
The system of claim 4, wherein the memory pool is a multi-headed device (MHD) having one or more ports configured to support CXLs and CXL-enabled connections with each of the plurality of sockets. Norman, Fog. 7, multi-ports memory 100 connects to CPUs via CXL channels.
Regarding claim 6:
The system of claim 4, wherein each of the respective plurality of sockets of each of the one or more multi-CPU-socket chassis is configured to transmit a page or cache line to subsequent multi-CPU-socket chassis via one or more inter-socket links of a respective inter- socket link application-specific integrated circuit (ASIC) of each of the one or more multi-CPU- socket chassis. Van Doren, Figs. 2-4, plurality of sockets are connected via interconnect fabric (0040, 0042), and data is exchanged between socket (¶0061, ¶0063, ¶0071, ¶0073).
Regarding claim 7:
The system of claim 5, wherein the memory pool is located in the first multi-CPU-socket chassis. Van Doren suggests any CPU may access the memory pool 302, and the memory 302 can be coupled or located on its socket (¶0061). Shalf also discloses the main memory maybe external or internal to the multi-core processor (3:45-55).
Regarding claim 8:
The system of claim 5, wherein the memory pool is located in a separate circuitry. Van Doren suggests any CPU may access the memory pool 302, and the memory 302 can be coupled or located on its socket (¶0061). Shalf also discloses the main memory maybe external or internal to the multi-core processor (3:45-55).
Regarding claim 12:
The system of claim 5, wherein the memory pool comprises a controller configured to receive a page or cache line from or transmit the page or cache line to a respective plurality of sockets of a multi-socket CPU chassis. Van Doren discloses (Fig. 4) memory controller 418 receives read/write or Fill command from the CPU from socket S0 (¶0071-0073).
Regarding claim 20:
The method of claim 19, wherein each of the plurality of sockets is connected to the memory pool via a Compute Express Link (CXL). The combination of Van Doren does not teach the claimed limitation above. However, in an analogous art of memory management, Norman, Fig. 7, suggest a shared memory 110 connects to plurality of CPU 110-1 to 110-8 using CXL channels (¶0071). One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Norman into the combination of Van Doren to obtain the claimed limitation above. The motivation for doing so is to apply a known technique, taught by Norman, into the system ready for improvement of Van Doren to yield predictable results.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Van Doren et al (U.S. 2004/0066758), Shalf et al (U.S. 10,102,179), and in view of Michaud et al (U.S. 10,459,852), and further in view of Kreinin et al (U.S. 11,294,815).
Regarding claim 9:
The system of claim 1, wherein the migrated allocated memory resource is a joint page accessible by the plurality of processing units in a joint computing process. Shalf discloses the multiple-core processor 100 can support a rich threading model with ultra-lightweight mechanisms for control and spawning of threads next to data (Shalf, 14:30-40). The multiple-core processor 100 is designed as a massively parallel system implemented as a network of chips each with an array of interconnected processing elements (PE) that can efficiently access global memory on a shared I/O fabric, or operate on local, per core memory for higher performance (10:40-55).
However, the combination of Van Doren does not disclose the migrated allocated memory resource is a joint page accessible by the plurality of processing units in a joint computing process. In an analogous art of multi-core processors system, Kreinin discloses a multiple multithreaded processors with shared data cache (abstract). Kreinin discloses a multi-core processor can execute instructions contained within a software program in parallel with one another (10:45-50); and Fig. 13A, at least two different processors obtain a same data from external memory, or Fig. 14, processors 1901/1902 write their cache data into external memory, the cached data maybe in the same for both caches, 39:30-50.(e.g. a joint data accessible by the plurality of processors in a parallel processing unit)
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Kreinin into the teaching of Van Doren to have a joint data accessible by the plurality of processing units in a joint computing process. The motivation for doing so is to apply a known technique, of Kreinin, into the system ready for improvement of Van Doren to yield predictable result.
Claim 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Van Doren et al (U.S. 2004/0066758), Shalf et al (U.S. 10,102,179), and in view of Michaud et al (U.S. 10,459,852), and further in view of Blinzer et al (U.S. 10,007,464).
Regarding claim 16:
The system of claim 1, wherein the migration is handled by an operating system associated with the plurality of processing units, including the first processing unit. The combination of Van Doren does not teach the claimed limitation above. However, in an analogous art of memory management, Blinzer (abstract) discloses the idea that an operating system (OS) can updates cache and flushes the cache content to backend storage (3:20-45). Blinzer discloses in Fig. 1, a plurality of solid-state graphics cards 110, each includes a plurality of processing units (dGPU 130), local memories 132, memory pool 135, which analogous to the multi-core socket of Van Doren. One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to incorporate the teaching of Blinzer to have an OS manages operation in a memory system. The motivation for doing so is to apply a known technique, of Blinzer, into a system ready for improvement of Van Doren to yield predictable result.
Regarding claim 17:
The system of claim 16, wherein the migrated allocated memory resource is maintained by the operating system and owned by the plurality of processing units. The combination of Van Doren suggests the migrated allocated memory resource, or flushed cache data is visible to all processors as cited above. Blinzer suggests the OS manages the cache flush operation to memory. Thus, one ordinary skill in the art would be able to derive from Blinzer and Van Doren to have the migrated allocated memory resource maintained by the OS and owned by the plurality of processing units.
Allowable Subject Matter
Claims 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Abraham et al (U.S. 2022/0004439) discloses a system on chip (SoC) comprises an inter-connected processor clusters.
Goodman et al (U.S. 2020/0125411) discloses a multi-socket computer system.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHOA D DOAN/Primary Examiner, Art Unit 2133 Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHOA D DOAN whose telephone number is (571)272-5950. The examiner can normally be reached Mon-Fri 1000-1700.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ROCIO DEL MAR PEREZ-VELEZ can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHOA D DOAN/Primary Examiner, Art Unit 2133
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