DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 is objected to because of the following informalities: in the limitation “wherein the shield pattern…contacts the second electrode through holes formed in the second layer…” should read “ wherein the shield pattern…contacts the second electrode through holes formed in the second insulation layer…” Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2020/0286927) in view of Kim et al. (US 2021/0125543),
As to Claim 9, Park et al. discloses A display device, comprising: a substrate (fig.14; substrate 101; para.0091,0141); a first insulation layer on the substrate (fig.14; insulating layer 102; para.0097,0142); a shield pattern on the first insulation layer (fig.14; metal layer 161 may be a layer for blocking light; para.0093); a second insulation layer on the first insulation layer (fig.6,14; insulating layer 160; para.0142),
a third insulation layer on the second insulation layer;
a first electrode and a second electrode of a driving transistor on the third insulation layer (fig.14; drain electrode 151 and source electrode 141; para.0090);
a drain node on the second insulation layer, contacting the first electrode, and overlapping the shield pattern (fig.14, contact hole CT2 contacting drain electrode 151 and drain region 131b; para.0111,0113),
a source node on the second insulation layer, contacting a second electrode contacting the shield pattern, and overlapping the shield pattern (fig.14, contact hole CT1 contacting source electrode 141 and source region 131a; para.0111,0113);
an active layer, disposed same layer of the drain node and the source node, between the drain node and the source node (fig.14; channel region 131c disposed between drain node at source region 131b and source node at source region 131a); and
a light emitting element including a pixel electrode contacting the second electrode, an intermediate layer on the pixel electrode, and a common electrode on the intermediate layer (fig.14, light emitting element EL including first electrode 191 (pixel electrode) contacting source electrode 141, organic emitting layer 192 (intermediate layer) , and second electrode (common electrode; para.0121-0123) ,
wherein as a voltage input to the drain node increases, a voltage of the source node increases and, as the voltage of the source node increases, a voltage of the pixel electrode increases, and
wherein after a data voltage is applied to the source node, and before the intermediate layer emits light, a common voltage is applied to the drain node, and
wherein the shield pattern overlaps the first electrode ,the second electrode, and the active layer, and contacts the second electrode through holes formed in the second layer, and the third insulating layer (fig.14, metal layer 161 overlaps drain electrode 151, source electrode 141, and active layer 131, and contacts source electrode 141 via hole CT5 formed passing through insulating layer 160 and insulating layer 102).
Park et al. does not expressly disclose a third insulation layer on the second insulation layer.
However, Park et al. discloses where second insulating layer 160 may be multilayer (para.0167).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al., by implementing insulating layer 160, as a multilayer insulation layer, such that a first layer of the multilayer insulating layer 160 would constitute the second insulation layer on the first insulation layer (102) and second layer of the multilayer insulating layer 160 constitute a third insulation layer on the second insulation layer. The motivation being since in doing so would not have modified the operation of the device, yielding predictable results.
Park et al. discloses does not expressly disclose wherein as a voltage input to the drain node increases, a voltage of the source node increases and, as the voltage of the source node increases, a voltage of the pixel electrode increases, and wherein after a data voltage is applied to the source node, and before the intermediate layer emits light, a common voltage is applied to the drain node.
Kim et al. discloses wherein as a voltage input to the drain node increases, a voltage of the source node increases and, as the voltage of the source node increases, a voltage of the pixel electrode increases (fig.2B, para.0098,0103-014), wherein after a data voltage is applied to the source node (fig.3- period P2; para.0125) and before the intermediate layer emits light (fig.3A, period P4; para.0132), a common voltage is applied to the drain node (fig.2B-3A; period P3, node N1 receives a bias driving voltage as transistor M4 is turned on; para.0081, 0129).
It would have been obvious to one ordinary skill in the art before the effective filing date of the
claimed invention to modify the device of Park et al. with the teachings of Kim et al, such that an on-bias
period (P3 of Kim543) may be inserted between the data programming phase and the emission phase
(of Lin), during which the second node (Node1) may receive a diving voltage as a scan transistor is
turned on. The motivation being so that hysteresis deviation between pixels may be removed (or
reduced).
As to Claim 10, Park et al. in view of Kim et al. disclose wherein the active layer includes an oxide semiconductor material (Park-para.0100).
As to Claim 11, Park et al. in view of Kim et al. disclose, wherein an overlap area between the shield pattern and the source node is configured to enhance capacitive coupling relative to an overlap area with the drain node (Park-para.0143).
As to Claim 12, Park et al. in view of Kim et al. disclose wherein the common voltage applied to the drain node before light emission is lower than a driving voltage supplied during light emission (Kim-para.0098, 0101-0102).
Allowable Subject Matter
Claims 1,5-8, 13, 16-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent Claims 1, 8, 13,18,20 are amended to include previously indicated allowable subject of Claims 4,8,15,18,20 (and its intervening claims), and are allowable over the prior art of record for the reasons noted in office action 03/24/2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) 9 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DISMERY MERCEDES/ Primary Examiner, Art Unit 2627
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