DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shi (US 9,805,773) in view of Xu (US 11,438,199).
Regarding claim 1, fig. 2-4 and 6 of Shi discloses a duty cycle correction circuit comprising: a duty adjustment circuit [240] configured to adjust phases of a clock signal [input to 240] according to a plurality of codes [ctrl] to generate a duty correction clock signal [output of 240]; and a duty control circuit [in 250 outputting ctrl] configured to control a first correction operation of finding and fixing an optimal value of a first code [e.g. coarse code] among the plurality of codes and a second correction operation of finding and fixing an optimal value of a second code [e.g. fine code] among the plurality of codes, wherein the duty control circuit is configured to, in each of a plurality of cycles during which the first correction operation is performed, change the first code by a basic unit within a first adjustable range and change the second code by a maximum value within a second adjustable range (fig. 6 describes adjusting the codes within the respective ranges for the coarse and fine codes). Shi does not disclose a plurality of external clock signals and a plurality of duty correction clock signals. However, Xu discloses a duty cycle corrector receiving a plurality of clock signals and outputting a plurality of plurality of corrected signals (col. 3, lines 46-51). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the plurality of clocking as taught in Xu for the purpose of utilizing a suitable and well-known type of clocking implementation.
Regarding claim 2, the combination as indicated above discloses wherein the duty adjustment circuit comprises: a first duty adjustment circuit [of 240 receiving a first clock of the plurality of clocks] configured to adjust a phase of a first external clock signal among the plurality of external clock signals according to the first code and the second code to generate a first duty correction clock signal among the plurality of duty correction clock signals; and a second duty adjustment circuit [of 240 receiving a second clock of the plurality of clocks] configured to adjust a phase of a second external clock signal among the plurality of external clock signals according to a third code and a fourth code among the plurality of codes to generate a second duty correction clock signal among the plurality of duty correction clock signals.
Regarding claim 5, the combination as indicated above discloses a duty detection circuit [of 250] configured to detect phase differences of the multi-phase clock signals to generate a plurality of duty detection signals, and configured to provide the plurality of duty detection signals to the duty control circuit.
Regarding claim 6, the combination as indicated above discloses wherein, when the second code is in an adjustable state in a process of performing the first correction operation, the duty control circuit is configured to change the second code by the maximum value within the second adjustable range, and configured to change the first code by the basic unit within the first adjustable range afterward (fig. 6 when further adjustment is needed because the clock duty cycle does not meet specs yet).
Regarding claim 7, the combination as indicated above discloses when the second code is in an unadjustable state in a process of performing the first correction operation, the duty control circuit is configured to change the first code by the basic unit within the first adjustable range, and configured to change the second code by the maximum value within the second adjustable range afterward (fig. 6 when further adjustment is not needed because the clock duty cycle meets specs).
Regarding claim 8, the combination as indicated above discloses wherein the duty control circuit is configured to, in each of a plurality of cycles during which the second correction operation is performed, change the second code by a basic unit within the second adjustable range.
Regarding claim 9, the combination as indicated above discloses wherein the duty control circuit is configured to selectively control the first duty adjustment circuit and the second duty adjustment circuit, wherein the first code and the second code are adjusted when the first duty adjustment circuit is selected, and wherein the third code and the fourth code are adjusted when the second duty adjustment circuit is selected (fig. 6).
Allowable Subject Matter
Claims 10-22 are allowed.
Claims 3 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Minzoni describes a duty cycle detector with oscillating signals. Ma describes duty cycle adjustment. Yang describes a duty cycle correction device. Addepalli describes a duty cycle and skew corrector.
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/SIBIN CHEN/Primary Examiner, Art Unit 2836
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