DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 4 of U.S. Patent No. 12,380,861. Although the Claims at issue are not identical, they are not patentably distinct from each other because the reference application Claim anticipates the examined application Claim.
MPEP 804.II.B.2 states: nonstatutory double patenting rejection is appropriate where a claim in an application under examination claims subject matter that is different, but not patentably distinct, from the subject matter claimed in a prior patent or a copending application. The claim under examination is not patentably distinct from the reference claim(s) if the claim under examination is anticipated by the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 1052, 29 USPQ2d 2010, 2015-16 (Fed. Cir. 1993).
19/238,810
(Examined Application)
US Patent 12,380,861
(Reference Application)
1. A display driver, comprising:
a first source output coupled to a display panel;
a second source output coupled to the display panel;
a first source amplifier configured to:
provide a first data voltage to the first source output based on first pixel data during a display update period; and
provide a predetermined voltage to the first source output during a non-display update period;
a second source amplifier configured to:
provide a second data voltage to the second source output based on second pixel data during the display update period; and be deactivated during the non-display update period; and
a first switch configured to electrically connect an output of the first source amplifier to the second source output
to provide the predetermined voltage to the second source output during the non-display update period; wherein
the predetermined voltage is higher than a high-side power supply voltage provided to pixels of the display panel.
4. A display driver, comprising:
a first source output coupled to a display panel;
a second source output coupled to the display panel;
a first source amplifier configured to:
provide a first data voltage to the first source output based on first pixel data during a display update period; and
provide a predetermined voltage to the first source output during a non-display update period, wherein
the predetermined voltage corresponds to a voltage level which reduces charge leakage from storage capacitors of pixels of the display panel during the non-display update period, the pixels being coupled to the first and second source outputs;
a second source amplifier configured to:
provide a second data voltage to the second source output based on second pixel data during the display update period; and be deactivated during the non-display update period; and
a first switch configured to electrically connect an output of the first source amplifier to the second source output
to provide the predetermined voltage to the second source output during the non-display update period, wherein
the predetermined voltage is higher than a high-side power supply voltage provided to pixels of the display panel.
Allowable Subject Matter
Claims 1-20 are allowed over the prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 contains the following subject matter that is neither taught nor suggested by the prior art, either alone or in combination:
a display driver, wherein
the predetermined voltage is higher than a high-side power supply voltage provided to pixels of the display panel.
Claim 9 contains the following subject matter that is neither taught nor suggested by the prior art, either alone or in combination:
a display device, wherein
the predetermined voltage is higher than a high-side power supply voltage provided to pixels of the display panel.
Claim 16 contains the following subject matter that is neither taught nor suggested by the prior art, either alone or in combination:
a method, wherein
the predetermined voltage is higher than a high-side power supply voltage provided to pixels of the display panel.
The following table provides differences between the claimed subject matter and subject matter taught by the prior art.
Claimed Subject Matter [Prior Art Teaching]
Difference
Claim 1 (Original), Kim (US 2016/0098966) teaches a display driver, comprising:
a first source output [fig. 9 @141] coupled to a display panel [fig. 9 @20];
a second source output [fig. 1 @142] coupled to the display panel [¶0041, “The output buffers 351 and 352 output the data voltages OUT1 and OUT2 to the corresponding data lines through the output terminals 141 and 142, respectively”];
a first source amplifier [fig. 2 @321] configured to: provide a first data voltage [fig. 3 @OUT1] to the first source output [fig. 1 @141] based on first pixel data [¶0028, “… The DAC 340 receives the plurality of gamma voltages GB1 to GBm, and outputs a gamma voltage corresponding to the gradation value of digital video data among the gamma voltages GB1 to GBm. The output buffer unit 350 buffers the gamma voltage outputted from the DAC 340, and provides the buffered gamma voltage as data voltages OUT1 to OUTn to the output terminals 141 to 146”] during a display update period [¶0076, “… Referring to FIGS. 6 to 8, a first period I may correspond to the normal display period, and a second period II may correspond to the blank period”, ¶0077 During the first period I, the first power down signal GPD and the second power down signal OPD are disabled (for example, low level). Thus, the gamma buffers 321 to 326 and the output buffers 351 to 356 perform a normal operation”]; and
provide a predetermined voltage [fig. 2 @SG] to the first source output [fig. 1 @141] during a non-display update period [fig. 8 @II];
a second source amplifier [fig. 2 @322] configured to:
provide a second data voltage [fig. 3 @OUT2] to the second source output [fig. 1 @142] based on second pixel data during the display update period [¶0076 and ¶0077]; and be deactivated during the non-display update period [¶0051, “during the blank period, a small number of gamma buffers (for example, 321) may be used to provide the same voltage to a large number of output terminals (for example, all of the output terminals 141 and 142). Since the other gamma buffers 322 and 323 and all of the output buffers 351 and 352 enter the power down mode, the power consumption of the blank period can be minimized”]; and
a first switch [fig. 3 @371] configured to electrically connect an output of the first source amplifier [fig. 2 @321] to the second source output [fig. 1 @142] to provide the predetermined voltage [fig. 3 @SG] to the second source output [fig. 1 @142] during the non-display update period [fig. 8 @II, ¶0045, “the first charge sharing switch 371 may couple the output terminals 141 and 142 corresponding to the pair of output buffers 351 and 352 which are driven in different driving ranges, such that the selected gamma voltage SG is shared by the output terminals 141 and 142”]
None
None
wherein the predetermined voltage is higher than a high-side power supply voltage provided to pixels of the display panel.
Not taught by the prior art
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Douglas Wilson whose telephone number is (571)272-5640. The examiner can normally be reached 1100-1800 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Douglas Wilson/Primary Examiner, Art Unit 2622