DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: DISPLAY SUBSTRATE AND DISPLAY DEVICE HAVING COMPENSATION SIGNAL LINES COUPLED TO INITIALIZATION SIGNAL BUSES.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time-wise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based e-Terminal Disclaimer may be filled out completely online using web-screens. An e-Terminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about e-Terminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-2 and 4-7 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 2 and 10-13 of Patent No. 12,369,471. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application claim is broader in every aspect than the patent claim and is therefore an obvious variant thereof:
Present Application
Patent
1. A display substrate, comprising:
a base substrate and a plurality of sub-pixels onto the base substrate, wherein the sub-pixel comprises:
a first initialization signal line and a second initialization signal line, wherein a potential of a first initialization signal transmitted by the first initialization signal line is different from a potential of a second initialization signal transmitted by the second initialization signal line; and
a sub-pixel driving circuit and a light-emitting element, wherein the sub-pixel driving circuit comprises a drive transistor, a first reset transistor and a second reset transistor;
a first electrode of the first reset transistor is coupled to a gate electrode of the drive transistor, and a second electrode of the first reset transistor is coupled to the first initialization signal line;
a first electrode of the second reset transistor is coupled to the light-emitting element, and a second electrode of the second reset transistor is coupled to the second initialization signal line;
wherein at least part of the first initialization signal line extends in a first direction;
at least part of the second initialization signal line extends in the first direction;
the sub-pixel further comprises:
a first compensation signal line and/or a second compensation signal line;
the first compensation signal line is coupled to the first initialization signal line, at least part of the first compensation signal line extends in a second direction, the second direction intersecting the first direction;
the second compensation signal line is coupled to the second initialization signal line, and at least part of the second compensation signal line extends in the second direction.
1. A display substrate, comprising:
a base substrate and a plurality of sub-pixels onto the base substrate, wherein the sub-pixel comprises:
a first initialization signal line and a second initialization signal line, wherein a potential of a first initialization signal transmitted by the first initialization signal line is different from a potential of a second initialization signal transmitted by the second initialization signal line; and
a sub-pixel driving circuit and a light-emitting element, wherein the sub-pixel driving circuit comprises a drive transistor, a first reset transistor and a second reset transistor;
a first electrode of the drive transistor is coupled to the light-emitting element;
a first electrode of the first reset transistor is coupled to a gate electrode of the drive transistor, and a second electrode of the first reset transistor is coupled to the first initialization signal line;
a first electrode of the second reset transistor is coupled to the light-emitting element, and a second electrode of the second reset transistor is coupled to the second initialization signal line;
wherein at least part of the first initialization signal line extends in a first direction;
at least part of the second initialization signal line extends in the first direction;
the sub-pixel further comprises:
a first compensation signal line and/or a second compensation signal line;
the first compensation signal line is coupled to the first initialization signal line, at least part of the first compensation signal line extends in a second direction, the second direction intersecting the first direction;
the second compensation signal line is coupled to the second initialization signal line, and at least part of the second compensation signal line extends in the second direction.
2. The display substrate according to claim 1, wherein the sub-pixel further comprises:
a data line, at least part of the data line extending in the second direction;
in a same one of the sub-pixels, an orthographic projection of a gate electrode of the drive transistor onto the base substrate is located between an orthographic projection of the data line onto the base substrate and an orthographic projection of the first compensation signal line onto the base substrate.
2. The display substrate according to claim 1, wherein the sub-pixel further comprises:
a data line, at least part of the data line extending in the second direction;
in a same one of the sub-pixels, an orthographic projection of a gate electrode of the drive transistor onto the base substrate is located between an orthographic projection of the data line onto the base substrate and an orthographic projection of the first compensation signal line onto the base substrate; and is located …
4. The display substrate according to claim 2, wherein the sub-pixel further comprises:
a data line, at least part of the data line extending in the second direction;
in a same one of the sub-pixels, an orthographic projection of the data line onto the base substrate is located between an orthographic projection of the gate electrode of the drive transistor onto the base substrate and an orthographic projection of the first compensation signal line onto the base substrate.
10. The display substrate according to claim 1, wherein the sub-pixel further comprises:
a data line, at least part of the data line extending in the second direction;
in a same one of the sub-pixels, an orthographic projection of the data line onto the base substrate is located between an orthographic projection of the gate electrode of the drive transistor onto the base substrate and an orthographic projection of the first compensation signal line onto the base substrate; and is located …
5. The display substrate according to claim 2, wherein the plurality of sub-pixels are distributed in an array, and in sub-pixels in the same row in the first direction, first initialization signal lines are coupled;
in sub-pixels in the same column in the second direction, first compensation signal lines are coupled;
and/or, in the sub-pixels in the same row in the first direction, second initialization signal lines are coupled;
in the sub-pixels in the same column in the second direction, the second compensation signal lines are coupled.
11. The display substrate according to claim 1, wherein the plurality of sub-pixels are distributed in an array, and in sub-pixels in the same row in the first direction, first initialization signal lines are coupled;
in sub-pixels in the same column in the second direction, first compensation signal lines are coupled;
and/or, in the sub-pixels in the same row in the first direction, second initialization signal lines are coupled;
in the sub-pixels in the same column in the second direction, the second compensation signal lines are coupled.
6. The display substrate according to claim 5, wherein the display substrate comprises a display area and a peripheral area surrounding the display area;
the display substrate further comprises:
a first initialization signal bus, wherein the first initialization signal bus is arranged in the peripheral area, at least part of the first initialization signal bus extends in the second direction, and the first initialization signal line is coupled to the first initialization signal bus; and/or
a second initialization signal bus, wherein the second initialization signal bus is arranged in the peripheral area, at least part of the second initialization signal bus extends in the second direction, and the second initialization signal line is coupled to the second initialization signal bus.
12. The display substrate according to claim 11, wherein the display substrate comprises a display area and a peripheral area surrounding the display area;
the display substrate further comprises:
a first initialization signal bus, wherein the first initialization signal bus is arranged in the peripheral area, at least part of the first initialization signal bus extends in the second direction, and the first initialization signal line is coupled to the first initialization signal bus; and/or
a second initialization signal bus, wherein the second initialization signal bus is arranged in the peripheral area, at least part of the second initialization signal bus extends in the second direction, and the second initialization signal line is coupled to the second initialization signal bus.
7. The display substrate according to claim 6, wherein the first initialization signal bus surrounds the display area;
the first compensation signal line is coupled to the first initialization signal bus; and/or
the second initialization signal bus surrounds the display area;
the second compensation signal line is coupled to the second initialization signal bus.
13. The display substrate according to claim 12, wherein the first initialization signal bus surrounds the display area;
the first compensation signal line is coupled to the first initialization signal bus; and/or
the second initialization signal bus surrounds the display area;
the second compensation signal line is coupled to the second initialization signal bus.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites the sub-pixel further comprises : “a first compensation signal line and/or a second compensation line; the first compensation line is coupled to … ; the second compensation signal line is coupled to ”. That is, the sub-pixel may comprise one or two compensation line(s): (1) If the sub-pixel comprises two “compensation lines”, claim 1 should recite only “and
Examiner suggests clearly reciting the number of the “compensation signal line” recited in claim 1, i.e., either one or two, and amend claim 1 accordingly. For the purpose of compact prosecution only, Examiner interprets it as “or”, i.e., the sub-pixel comprises only one “compensation signal line”, i.e., “1st compensation signal line” is “2nd compensation signal line”, for the following claim rejections.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor.
Claim 4 recites the limitation “an orthographic projection of the data line onto the base substrate is located between an orthographic projection of the gate electrode of the drive transistor onto the base substrate and an orthographic projection of the first compensation signal line onto the base substrate”. However, such configuration does not match any embodiment shown in, e.g., FIGS. 2-5, 11 and 14-15 and their corresponding paragraphs, which depict “first/second compensation signal line(s) 21 22” and “data line 23”.
Accordingly, claim 4 is indefinite. There is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of claim 4, thus it would not be proper to reject such claims on the basis of prior art. As stated in In reSteele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims. Please see MPEP 2173.06 II.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 11-17 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Diao et al. (US 2021/0335989 A1).
As to claim 1, Diao discloses a display substrate (Diao, Abs., a “display substrate”), comprising:
a base substrate (Diao, FIG. 8, [0397], “base 50”) and a plurality of sub-pixels (Diao, FIG. 1, [0145], a plurality of “sub-pixels”) onto the base substrate (Diao, FIG. 8, [0397], “base 50”), wherein the sub-pixel (Diao, FIG. 1, [0145], the “sub-pixel”) comprises:
a first initialization signal line (Diao, FIG. 1, [0145], “first initialization signal line pattern VINT1,”) and a second initialization signal line (Diao, FIG. 1, [0145], “second initialization signal pattern VINT2”), wherein a potential of a first initialization signal transmitted by the first initialization signal line is different from a potential of a second initialization signal transmitted by the second initialization signal line (Diao, FIG. 1, [0189], “a first shielding member 404 coupled to the initialization signal line pattern (VINT1 in FIG. 3) in the sub-pixel driving circuit so that the first shielding member 404 has the same fixed potential as the initialization signal”: it is reasonably inferred that the potential of VINT2 may be different from the “fixed potential” given the structure of the VINT1 and VINT2 being separate electrodes as shown in, e.g., FIG. 3); and
a sub-pixel driving circuit (Diao, FIG. 1, [0146], “each of the sub-pixel driving circuits”) and a light-emitting element (Diao, FIG. 1, [0151], “light-emitting element OLED”), wherein the sub-pixel driving circuit (Diao, FIG. 1, [0146], “each of the sub-pixel driving circuits”) comprises a drive transistor (Diao, FIG. 1, [0146], “third transistor T3”), a first reset transistor (Diao, FIG. 1, [0148], “second transistor T2” coupled to “first reset signal pattern RST1”) and a second reset transistor (Diao, FIG. 1, [0152], “seventh transistor T7” coupled to “second reset signal line pattern RST2”);
a first electrode (Diao, FIG. 1, [0146], drain of “third transistor T3”) of the drive transistor (Diao, FIG. 1, [0146], “third transistor T3”) is coupled to (Diao, see FIG. 1, via “sixth transistor T6”) the light-emitting element (Diao, FIG. 1, [0151], “light-emitting element OLED”);
a first electrode (Diao, see FIG. 1) of the first reset transistor (Diao, FIG. 1, [0148], “second transistor T2” coupled to “first reset signal pattern RST1”) is coupled to (Diao, see FIG. 1) a gate electrode of the drive transistor (Diao, FIG. 1, [0146], “third transistor T3”), and a second electrode (Diao, see FIG. 1) of the first reset transistor (Diao, FIG. 1, [0148], “second transistor T2” coupled to “first reset signal pattern RST1”) is coupled to (Diao, see FIG. 1) the first initialization signal line (Diao, FIG. 1, [0145], “first initialization signal line pattern VINT1”);
a first electrode (Diao, see FIG. 1) of the second reset transistor (Diao, FIG. 1, [0152], “seventh transistor T7” coupled to “second reset signal line pattern RST2”) is coupled to (Diao, see FIG. 1) the light-emitting element (Diao, FIG. 1, [0151], “light-emitting element OLED”), and a second electrode (Diao, see FIG. 1) of the second reset transistor (Diao, FIG. 1, [0151], “light-emitting element OLED”) is coupled to (Diao, see FIG. 1) the second initialization signal line (Diao, FIG. 1, [0145], “second initialization signal pattern VINT2”);
wherein at least part of the first initialization signal line (Diao, FIG. 1, [0145], “first initialization signal line pattern VINT1”) extends in a first direction (Diao, FIG. 1, Examiner interprets the horizontal direction “X” as the 1st direction);
at least part of the second initialization signal line (Diao, FIG. 1, [0145], “second initialization signal pattern VINT2”) extends in the first direction (Diao, FIG. 1, the horizontal direction “X”);
the sub-pixel further comprises:
a first compensation signal line and/or a second compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”);
the first compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) is coupled to the first initialization signal line (Diao, see FIG. 9, [0197], “VINT1”), at least part of the first compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) extends in a second direction (Diao, see FIG. 3, Examiner interprets vertical direction “Y” as the 2nd direction), the second direction (Diao, see FIG. 3, vertical direction “Y”) intersecting the first direction (Diao, see FIGS. 1 and 3, the horizontal direction “X”);
the second compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) is coupled to the second initialization signal line (Diao, see FIG. 9, [0197], “VINT2”; “first shield member 404 is coupled to two adjacent ones of the initialization signal lines”), and at least part of the second compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) extends in the second direction (Diao, see FIG. 3, vertical direction “Y”).
As to claim 2, Diao discloses the display substrate according to claim 1, wherein the sub-pixel (Diao, FIG. 3, the sub-pixel of FIG. 3) further comprises:
a data line (Diao, FIG. 3, “DATA1”), at least part of the data line (Diao, FIG. 3, “DATA1”) extending in the second direction (Diao, see FIG. 3, in vertical “Y” direction);
in a same one of the sub-pixels (Diao, FIG. 3, the sub-pixel of FIG. 3), an orthographic projection of a gate electrode (Diao, FIG. 3, [0173], “gate 203g of the third transistor T3”) of the drive transistor (Diao, FIG. 1, [0146], “third transistor T3”) onto the base substrate (Diao, see FIG. 3) is located between an orthographic projection of the data line (Diao, FIG. 3, “DATA1”) onto the base substrate (Diao, see FIG. 3) and an orthographic projection of the first compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) onto the base substrate (Diao, see FIGS. 3 and 9).
As to claim 3, Diao discloses the display substrate according to claim 2, wherein the first compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) and the second compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) are arranged in a same layer (Diao, see FIG. 7 and 9, [0118], “a first layout of an active film layer”) and made of a same material as (Diao, see FIGS. 3-4, 7 and 9, [0161], , “the active film layer may be made of amorphous silicon, polysilicon, oxide semiconductor material, or the like”) the data line (Diao, see FIGS. 3-4, 7 and 9, “DATA1”).
As to claim 11, Diao discloses the display substrate according to claim 1, wherein the first initialization signal line (Diao, FIG. 6, “VINT1”) and the second initialization signal line (Diao, FIG. 6, “VINT2”) are arranged in a same layer (Diao, see FIG. 6, [0120], “first layout of a second gate metal layer”) and made of a same material (Diao, see FIG. 6, [0164], “As shown in FIG. 6, the second gate metal layer is used to form … VINT1 … and VINT2”).
As to claim 12, Diao discloses the display substrate according to claim 1, wherein the first compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) and the second compensation signal line (Diao, FIG. 9, [0197], “first shield member 404”) are arranged in the same layer and made of the same material (Diao, see FIGS. 7 and 9).
As to claim 13, Diao discloses the display substrate according to claim 1, wherein the first initialization signal line (Diao, FIG. 6, “VINT1”) is arranged in a different layer from (Diao, see FIGS. 6-7, [0121], “a first layout of a source-drain metal layer”) the first compensation signal line (Diao, FIGS. 7 and 9, [0197], “first shield member 404”; FIGS. 20-21, [0436], “the first shielding member 404 is at a different layer from the initialization signal line pattern”).
As to claim 14, Diao discloses the display substrate according to claim 13, wherein the orthographic projection of the first compensation signal line onto the base substrate (Diao, see FIGS. 20-21, [0436], “first shielding member 404”) and the orthographic projection of the first initialization signal line onto the base substrate (Diao, see FIGS. 20-21, [0436], “VINT1”) have a first overlap area (Diao, see FIGS. 20-21), the first compensation signal line (Diao, see FIGS. 20-21, [0436], “first shielding member 404”) and the first initialization signal line (Diao, see FIGS. 20-21, [0436], “VINT1”) are coupled through a first via hole (Diao, see FIGS. 20-21, [0436], “the first shielding member is coupled to the initialization signal line pattern through a first via-hole in the first overlapping region”), and an orthographic projection of the first via hole onto the base substrate is located within the first overlap area (Diao, see FIGS. 20-21).
As to claim 15, Diao discloses the display substrate according to claim 14, wherein the orthographic projection of the second compensation signal line onto the base substrate (Diao, see FIGS. 20-21, [0436], “first shielding member 404”) and the orthographic projection of the second initialization signal line onto the base substrate (Diao, FIGS. 20-21, [0436], “VINT2”) have a second overlap area (Diao, see FIGS. 20-21), the second compensation signal line and the second initialization signal line are coupled by a second via hole (Diao, see FIGS. 20-21, [0436], “the first shielding member is coupled to the initialization signal line pattern through a second via-hole in the second overlapping region”).
As to claim 16, Diao discloses the display substrate according to claim 1, wherein the first initialization signal lines (Diao, FIG. 9, “VINT1”) and the first compensation signal lines (Diao, FIG. 9, “first shielding member 404”) forms a grid-like structure (Diao, see, e.g., FIG. 9).
As to claim 17, Diao discloses the display substrate according to claim 2, wherein the sub-pixel driving circuit further includes a storage capacitor (Diao, FIGS. 1-6, “storage capacitor Cst”), the storage capacitor (Diao, FIGS. 1-6, “storage capacitor Cst”) includes a first plate (Diao, see FIGS. 1-6, “first electrode plate Cst2”) and a second plate arranged (Diao, see FIGS. 1-6, “second electrode plate Cst1”) opposite to each other (Diao, see FIGS. 1-6);
the sub-pixel further includes:
a light-emitting control signal line (Diao, FIGS. 1-7, “EM”);
an orthographic projection of the second plate onto the base substrate (Diao, see FIGS. 1-7, “203g(Cst1)”) does not overlap (Diao, e.g., see FIG. 3) the orthographic projection of the data line onto the base substrate (Diao, FIGS. 1-7, “DATA1”);
the orthographic projection of the second plate onto the base substrate (Diao, see FIGS. 1-7, “203g(Cst1)”) does not overlap (Diao, e.g., see FIG. 5) an orthographic projection of the light-emitting control signal line onto the base substrate (Diao, FIG. 5, “EM”).
As to claim 20, it differs from claim 1 only in that it is the display device comprising the display substrate of claim 1. It recites substantially the same limitations as in claim 1, and Diao discloses them. Please see claim 1 for detailed analysis.
Allowable Subject Matter
Claim 5-10 and 18-19 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5, Diao in view of Yu (US 2022/0122547 A1) teaches the display substrate according to claim 2, wherein the plurality of sub-pixels are distributed in an array, and in sub-pixels in the same row in the first direction (Yu, see FIG. 2B), first initialization signal lines are coupled (Yu, see FIG. 2B, [0075], “the initialization bus 34 is electrically connected to the plurality of initialization lines 17 located at the display area 111”); in sub-pixels in the same column in the second direction (Yu, see FIG. 2B).
However, the closest known prior art, i.e., Diao et al. (US 2021/0335989 A1), Yu (US 2022/0122547 A1), Liu (US 2023/0097504 A1) and Cho et al. (US 2021/0359058 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “first compensation signal lines are coupled”.
As to claims 6-8, they directly or indirectly depend from claim 5, and are allowable at least for the same reason above.
As to claim 9, Diao teaches the display substrate according to claim 3, wherein the sub-pixel (Diao, FIGS. 3-4, the sub-pixel in FIGS. 3-4) further comprises:
a first reset signal line (Diao, see FIGS. 3-4, “RST1”), and at least part of the first reset signal line (Diao, see FIGS. 3-4, “RST1”) extends in the first direction (Diao, see FIGS. 3-4, horizontal “X” direction);
the first reset transistor (Diao, FIGS. 3-4, “T2”) comprises a first active pattern (Diao, see FIGS. 3-4, “gate 202g, drain formation region 102pd, source formation region 102ps”);
wherein the first active pattern (Diao, see FIGS. 3-4, “gate 202g, drain formation region 102pd, source formation region 102ps”) comprises the first electrode (Diao, see FIGS. 3-4, “drain formation region 102pd”) and the second electrode (Diao, see FIGS. 3-4, “source formation region 102ps”) of the first reset transistor (Diao, FIGS. 3-4, “T2”);
the sub-pixel (Diao, FIGS. 3-4, the sub-pixel in FIGS. 3-4) further comprises:
a first conductive connecting part (Diao, see FIGS. 3-4, [0214], “first extension” including “first portion 61, second portion 62, third portion 63”), and the first conductive connecting part (Diao, see FIGS. 3-4, [0214], “first extension”) comprises a first portion and a second portion (Diao, see FIGS. 3-4).
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “the first portion is coupled to the first initialization signal line and the first compensation signal line, and the second portion is coupled to the second electrode of the first reset transistor”.
As to claim 10, Diao teaches the display substrate according to claim 3, wherein the sub-pixel further comprises:
a second reset signal line (Diao, FIG. 9, “RST2”), and at least part of the second reset signal line (Diao, FIG. 9, “RST2”) extends in the first direction (Diao, FIG. 9, horizontal “X” direction);
the second reset transistor (Diao, see FIGS. 3 and 9, “T7”) comprises a second active pattern (Diao, FIG. 9, [0172], T7 comprising “channel region 107pg”, “source formation region 107ps”, “drain formation region 107pd”);
wherein the second active pattern comprises the first electrode and the second electrode of the second reset transistor (Diao, FIG. 9, [0172], T7 comprising “channel region 107pg”, “source formation region 107ps”, “drain formation region 107pd”).
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “a second conductive connecting part, the second conductive connecting part comprises a third portion and a fourth portion, the third portion is coupled to the second initialization signal line and the second compensation signal line, and the fourth portion is coupled to the second electrode of the second reset transistor; the display substrate further includes a first source and drain metal layer; the second conductive connecting part is arranged in a same layer and made of a same material as the first source and drain metal layer”.
As to claim 18, Diao teaches the display substrate according to claim 2, wherein the sub-pixel further includes:
a power supply line (Diao, FIGS. 1-3, “VDD”);
the power supply line includes a first power supply pattern (Diao, see FIG. 3, “power supply signal line pattern VDD”);
the sub-pixel further includes:
a compensation transistor (Diao, FIG. 1, [0156], “transistor T1”) including a third active pattern (Diao, e.g., FIG. 3, [0166], T1 pattern comprising “drain forming 101pd”, “source forming pattern 101ps”, “gate 201g”);
a storage capacitor (Diao, FIG. 1, “storage capacitor Cst”), where the storage capacitor includes a first plate (Diao, FIG. 1, “Cst1”) and a second plate (Diao, FIG. 1, “Cst2”) that are oppositely arranged (Diao, see FIGS. 1-6), the second plate includes a plate body (Diao, FIG. 6, Examiner interprets the body part of “Cst” comprising a hole at the center as the “plate body”) and a plate shielding part (Diao, FIG. 6, Examiner interprets the left protrusion of “Cst” as the “plate shielding part”);
an orthographic projection of the plate shielding part onto the base substrate (Diao, FIG. 6, the left protrusion of “Cst”) does not overlap (Diao, see FIG. 9) the orthographic projection of the first compensation signal line onto the base substrate (Diao, FIG. 9, “first shielding member 404”);
and/or the orthographic projection of the plate shielding part onto the base substrate does not overlap the orthographic projection of the second compensation signal line onto the base substrate.
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitation “an orthographic projection of the first power supply pattern onto the base substrate partially overlaps the orthographic projection of the data line onto the base substrate”.
As to claim 19, it depends from claim 10, and is allowable at least for the same reason above.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure: Liu (US 2023/0097504 A1) teaches the concept of a “display substrate … include … reset signal line … initialization signal line” (Abs.); Yu (US 2022/0122547 A1) teaches the concept of “initialization signal line bus 34” (e.g., FIG. 2B); and Cho et al. (US 2021/0359058 A1) teaches the concept of “substrate having a sub-pixel circuit … an active pattern … and a straight portion … and a sub-pixel structure on the active pattern” (Abs.).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Mar. 14, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2623
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