Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of informalities. The expressions “two wire, 2W, connection” and “four wire, 4W, connection” use improper punctuation and omit the hyphens required for compound modifiers. These expressions should be written as “two-wire (2W) connection” and “four-wire (4W) connection,” respectively, for grammatical clarity and consistent abbreviation formatting. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3 and 5 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ervin (US Pat. No. 20040225812) in view of Bui et al. (US Pub. No. 20060290381), hereinafter referred to as Bui.
As to claim 1, Ervin discloses a device comprising:
an I2C path section (Ervin: port-A interface 208 and port-B interface 214 connecting I2C domains 202 and 204, Fig. 2A, paras. 0030–0032) for realizing (Ervin: buffering and retransmitting I2C transactions between bus segments, para. 0027);
toward an application processor (Ervin: configuration-host processor communicating through the bridge hierarchy, paras. 0013, 0016, 0036, 0050) and a further device (Ervin: slave devices accessible through the I2C bridge, paras. 0016, 0027–0028, 0034);
a local I2C module (Ervin: I2C bridge implemented by microcontroller 201 having port-A interface 208 and port-B interface 214, Fig. 2A, paras. 0029–0032) connected to local I2C circuitry (Ervin: masters and slave devices associated with respective I2C domains, paras. 0027–0028, 0034, 0057) via a two wire, 2W, connection (Ervin: bidirectional SCL and SDA lines 206, 210, 212, and 216, Fig. 2A, para. 0032).
Bui discloses, what Ervin lacks, a 4W I2C path (Bui: physically separate send and receive paths for each SCL and SDA signal, providing two unidirectional signal paths in each direction, Figs. 1 and 4, paras. 0053, 0067–0070, 0082–0083);
wherein the I2C path section is provided as four wire, 4W, connection (Bui: physically separate send and receive paths for two identical buffers respectively carrying SCL and SDA, thereby providing an SCL and SDA pair in each transmission direction, Figs. 1 and 4, paras. 0053, 0067–0070);
wherein the local I2C module comprises a static voltage offset means (Bui: controlled offset-voltage circuits comprising offset voltages 132 and 133, amplifiers 130 and 135, and transistors 131 and 134, Fig. 4, paras. 0035–0037, 0081–0083) for converting (Bui: interface buffer propagating signals between physically separate forward and reverse paths and a bidirectional I2C signal path, Figs. 1 and 4, paras. 0022–0031, 0053, 0067–0070, 0082–0083) between unidirectional signals (Bui: signals carried over physically separate send and receive paths, para. 0053) carried in opposite directions (Bui: forward amplifier path 130–132 and reverse amplifier path 133–135, Fig. 4, paras. 0068, 0082–0083) over two 2W pairs of said 4W path (Bui: separate SCL and SDA send pair and separate SCL and SDA receive pair provided by the two identical clock and data buffers, Figs. 1 and 4, paras. 0053, 0067–0070) and bidirectional signals (Bui: I2C clock and data signals transmitted bidirectionally through the buffer, paras. 0001–0003, 0022–0031) carried over said 2W connection (Bui: SDA data wire and SCL clock wire of the bidirectional I2C channel, paras. 0003, 0008) toward the local I2C circuitry (Bui: I2C slave 53 connected through buffers 51 and 52, Fig. 2, paras. 0071–0075).
Ervin and Bui are analogous art because they are from the same field of endeavor, namely I2C bus interfacing, buffering, and extension between interconnected electronic devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Ervin and Bui before him or her, to modify the I2C bridge interfaces connecting the I2C bus domains of Ervin to include the physically separate send and receive signal paths and controlled voltage-offset buffer circuitry of Bui because Bui teaches separating the forward and reverse paths for each of the SCL and SDA signals, thereby providing respective SCL and SDA signal pairs traveling in opposite directions.
The suggestion/motivation for doing so would have been to extend the permissible physical length of Ervin’s I2C communication path, isolate the capacitance of the interconnected bus segments, improve signal integrity, and prevent latch-up or oscillation when signals change direction.
Therefore, it would have been obvious to combine Bui with Ervin to obtain the invention as specified in the instant claim.
As to claim 2, Ervin in view of Bui discloses device of claim 1, wherein the I2C path section is configured for realizing said 4W I2C path according to a daisy chain topology (Ervin: hierarchical path through multiple bridge devices toward downstream I2C devices, paras. 0016, 0027, 0050–0058; Bui: multiple I2C buffers connected in series to extend the communication path, Fig. 2, paras. 0017, 0035, 0071–0075) wherein the path extends between the application processor and the device, on the one hand (Bui: path from bus master 50 to first buffer 51, Fig. 2, paras. 0071–0074), and between the device and the further device, on the other hand (Bui: continued path from first buffer 51 through second buffer 52 to slave device 53, Fig. 2, paras. 0071–0075).
As to claim 3, Ervin discloses Device of claim 1, further comprising: an I2C repeater module (Ervin: unidirectional bridge implemented by microcontroller 201 having port-A interface 208 and port-B interface 214, Fig. 2A, paras. 0027–0032) for unidirectional repeating (Ervin: receiving an I2C transaction at port-A and retransmitting the transaction at port-B, paras. 0027–0028, 0074–0076) of said unidirectional signals (Ervin: address and data signals forwarded from one I2C bus segment to another, paras. 0027–0028, 0074–0076) carried over said path (Ervin: transactions carried between I2C domains 202 and 204 through bridge 201, Fig. 2A, paras. 0030–0032).
As to claim 5, Ervin discloses Device of claim 1, further comprising: an address translation module (Ervin: microcontroller 201 executing bridge software, address bitmap 240, registers 242, and command interpreter 244, Figs. 2A–2B, paras. 0027, 0030, 0035–0038) for providing address translation (Ervin: filtering, translating, replicating, and tunneling I2C addresses between bus segments, paras. 0012–0016, 0027, 0034, 0038–0041, 0074–0076) between a global address over said path (Ervin: bridge identifier and tunneled target address used across the bus hierarchy, paras. 0040–0041, 0060–0076) and a local I2C address for the local I2C circuitry (Ervin: locally replicated slave addresses assigned to respective bus segments and reached using bridge tunneling, paras. 0015, 0034, 0040–0041, 0057, 0060–0076).
As to claim 6, Ervin in view of Bui discloses Device of claim 5, wherein the address translation module (Ervin: microcontroller 201 implementing address translation using address bitmap 240, registers 242, and command interpreter 244, Figs. 2A–2B, paras. 0027, 0030, 0035–0041) is a 4W module (Bui: interface circuitry having physically separate send and receive paths for each of two identical buffers respectively carrying the SDA and SCL signals, thereby providing four unidirectional signal paths, Figs. 1 and 4, paras. 0053, 0067–0070; Ervin: address-processing microcontroller 201 positioned between and controlling the respective port-A and port-B interfaces, Fig. 2A, paras. 0029–0038) connected to the I2C path section (Ervin: microcontroller 201 connected to port-A interface 208 and port-B interface 214 for transferring I2C transactions between I2C domains 202 and 204, Fig. 2A, paras. 0030–0032) and the local I2C module (Ervin: address-processing functions, bridge software, and local I2C interfaces implemented by microcontroller 201, Figs. 2A–2B, paras. 0029–0038; Bui: bidirectional two-wire I2C circuitry interfaced with the physically separate send and receive paths, Figs. 1–2 and 4, paras. 0003, 0008, 0053, 0067–0075).
Allowable Subject Matter
Claims 4 and 7 – 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Walmsley (US Pub. No. 20060139681) disclosed a first entity including: a first bit-pattern a non-volatile memory storing resource data, a first base key for use with at least a first variant key; a second variant key for use with a second base key, the second variant key being the result of a one way function applied to: the second base key.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUANITO C BORROMEO whose telephone number is (571)270-1720. The examiner can normally be reached on Monday - Friday 9 - 5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 5712724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.B/ Assistant Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
