DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 21 – 45 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21 – 45 are rejected on the ground of nonstatutory double patenting as being
unpatentable over claims 1 - 20 of U.S. Patent No. 12332826 in view of Lanka et al (US20220222198) hereinafter Lanka, and in further view of Shukla et al (US20220311832) hereinafter Shukla.
The related patent (US12332826) teaches a means for two dies to communicate over a die-to-die link.
The port on a die includes physical layer circuitry plus a logical PHY that coordinates
the link. The physical layer is split into sideband lanes and mainband lanes. The sideband lanes carry training, setup, and management information, while the mainband lanes carry the main user data.
The present application is an application using this D2D infrastructure. It teaches a chip-to-chip communication port for connecting one die to another over a die-to-die link. The
link uses UCIe-based signaling and is split into sideband lanes and mainband lanes.
The related patent (US12332826) does not claim the (D2D) link compliant with a Universal Chiplet Interconnect Express (UCIe)-based protocol.
Lanka describes a way for two dies in the same package to talk over a die-to-die
interconnect. The link includes a main data path and a separate sideband path used for
setup, training, debugging, and status exchange with a Ucie link as the interconnect. It
also teaches the presence of a bridge device, such as a GPU (Fig. 12, and para. 0130),
which is an element in independent claims 34, and 37. It would have been obvious to one of ordinary skill in the art to combine the teaching of
Lanka with the related patent to achieve the application’s claimed functionality in the
independent claims for the Ucie protocol.
The table below illustrates the similar and contrasting elements of the present applicant
and the related patent.
Present Application
US 12332826
21. An apparatus comprising: a bridge device comprising: a port to couple to a die over a die-to-die (D2D) link compliant with a Universal Chiplet Interconnect Express (UCIe)-based protocol, (Lanka Fig. 2a, para. 0029)
wherein the port comprises: physical layer (PHY) circuitry comprising: a logical PHY; a first number of sideband lane pins, wherein the sideband lane pins are to carry data for use in training and management of the D2D link; and a second number of mainband lane pins, wherein the mainband lane pins are to implement a main data path of the D2D link, and the second number of mainband lane pins comprise forwarded clock, a data valid pin, and a plurality of data lane pins, wherein the logical PHY coordinates functions of the sideband lane pins and the mainband lane pins.
1. An apparatus comprising: a port to couple to another die over a die-to-die (D2D) link, wherein the port comprises: physical layer (PHY) circuitry comprising: a logical PHY; a first number of sideband lane pins, wherein the sideband lane pins are to carry data for use in training and management of the D2D link; and a second number of mainband lane pins, wherein the mainband lane pins are to implement a main data path of the D2D link, and the second number of mainband lane pins comprise forwarded clock, a valid lane pin, and a plurality of data lane pins, wherein the logical PHY coordinates functions of the sideband lane pins and the mainband lane pins.
34. An apparatus comprising: a chiplet comprising: graphics processing circuitry; and a port to couple to another die over a die-to-die (D2D) link compliant with a Universal Chiplet Interconnect Express (UCIe)-based protocol (Lanka Fig. 2a, para. 0029), wherein the port comprises: physical layer (PHY) circuitry comprising: a logical PHY; a first number of sideband lane pins, wherein the sideband lane pins are to carry data for use in training and management of the D2D link; and a second number of mainband lane pins, wherein the mainband lane pins are to implement a main data path of the D2D link, and the second number of mainband lane pins comprise forwarded clock, a data valid lane pin, and a plurality of data lane pins, wherein the logical PHY coordinates functions of the sideband lane pins and the mainband lane pins.
1. An apparatus comprising: a port to couple to another die over a die-to-die (D2D) link, wherein the port comprises: physical layer (PHY) circuitry comprising: a logical PHY; a first number of sideband lane pins, wherein the sideband lane pins are to carry data for use in training and management of the D2D link; and a second number of mainband lane pins, wherein the mainband lane pins are to implement a main data path of the D2D link, and the second number of mainband lane pins comprise forwarded clock, a valid lane pin, and a plurality of data lane pins, wherein the logical PHY coordinates functions of the sideband lane pins and the mainband lane pins.
37. A system comprising: a graphics processing unit (GPU); and a bridge device coupled to the GPU through a first interface, wherein the bridge device (Lanka teaches bridge device in Fig. 1, and para. 0024, and Fig. 2a, and bridge 225 between die ports, para. 0029) comprises a second interface to couple to another device, and the second interface is to couple to the other device over a die-to-die (D2D) link compliant with a Universal Chiplet Interconnect Express (UCIe)-based protocol, wherein the second interface comprises: physical layer (PHY) circuitry comprising: a logical PHY; a first number of sideband lane pins, wherein the sideband lane pins are to carry data for use in training and management of the D2D link; and a second number of mainband lane pins, wherein the mainband lane pins are to implement a main data path of the D2D link, and the second number of mainband lane pins comprise forwarded clock, a data valid pin, and a plurality of data lane pins, wherein the logical PHY coordinates functions of the sideband lane pins and the mainband lane pins.
17. A system comprising: a first die; and a second die coupled to the first die by a die-to-die (D2D) link, wherein the second die comprises a port to connect the second die to the D2D link, and the port comprises: protocol layer logic; die-to-die adapter circuitry; and physical layer circuitry, wherein the die-to-die adapter is positioned between the protocol layer logic and the physical layer circuitry and manages link states for the D2D link, and the physical layer circuitry comprises: a first number of sideband lanes for the D2D link, wherein the sideband lanes are to carry data for use in training and management of the D2D link; and a second number of mainband lanes for the D2D link, wherein the mainband lanes are to implement a main data path of the D2D link, and the second number of mainband lanes comprise a forwarded clock lane, a valid lane, and a plurality of data lanes
As to the dependent claims, the following double patent rejections are made.
As to claim 22, Lanka teaches the apparatus, wherein the main data path is to carry data for a graphics processor (Fig. 12, and para. 0130). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 23, and 35, Shukla discloses the apparatus, wherein the main data path is to carry data of a machine learning workload (Fig. 1, and para. 0027). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to deploy the devices of US12332826 in the system of Shukla to enable a scalable, multi-protocol efficient system (para. 0002).
As to claims 24, and 36, Shukla discloses the apparatus, wherein the main data path is to carry data of an artificial intelligence (AI) workload (Fig.1, and para. 0029). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to deploy the devices of US12332826 in the system of Shukla to enable a scalable, multi-protocol efficient system (para. 0002).
As to claim 25, Lanka discloses the apparatus, wherein the die comprises a second port to couple to another device (Fig. 1, and para. 0025). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claim 26, Lanka discloses the apparatus, wherein the other device comprises a GPU (para. 0130). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 27, and 39, Lanks discloses the apparatus, wherein the bridge device comprises protocol translation logic (Fig. 1, and para. 0025, for PCie to CXL translation module). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 28, and 40, Lanka discloses the apparatus, wherein the PHY circuitry further comprises an interface to communicatively couple to die-to-die adapter circuitry, wherein the die-to-die adapter circuitry is to facilitate data transfer between a protocol layer and a physical layer implemented using the PHY circuitry (para. 0024). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 29, and 41, Lanka discloses the apparatus, wherein the first number of sideband lane pins and the second number of mainband lane pins are organized into a module, and a physical layer of the D2D link is implemented as an integer multiple of one or more of the modules (para. 0136). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 30, and 42, Lanka discloses the apparatus, wherein the physical layer of the D2D link consists of a single module, and the single module is the first module (para. 0040). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 31, and 43, Lanka discloses the apparatus, wherein the physical layer of the D2D link comprises a plurality of instances of the module, and the logical PHY governs the plurality of instances of the module, wherein each module in the plurality of instances of the module comprises a respective first number of sideband lanes and second number of mainband lanes (Fig. 8, and para. 0088). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 32, and 44, Lanka discloses, wherein the sideband lanes operate in an always on domain (para. 0042). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claims 33, and 45, Lanka discloses the apparatus, wherein the logical PHY is to: manage training and transfers on the sideband lanes; and manage training of the mainband lanes, wherein the training of sideband lanes is separate from the training of mainband lanes (Fig. 7, and para. 0078). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
As to claim 38, Lanka discloses the system, further comprising a system on chip, and the system on chip comprises the bridge device (Fig. 12, and para. 0127). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the specifics application of Lanka in the system of US12332826 to provide a multi-protocol efficient die to die system (para. 0017).
Conclusion
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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