DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/16/25 was considered by the examiner.
Drawings
The drawings received on 6/16/25 have been accepted by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Throughout the claims, the numbers in parenthesis render the claim as indefinite because it is not clear what these numbers refer to. Clarification or removal required.
Claim 4, line 3, the limitations drawn to “a word line within group of the first type cells” is indefinite because it is unclear and undetermined what group is being referred to. It is possible that this limitation should read “the group” or “a group”. Clarification is required.
Claim 12, it is unclear what applicant intends to claim because the claim ends abruptly with “and” and no period. The claim appears to be incomplete.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu Cai et al., “Error Characterization, Mitigation, and Data Recovery in Flash Memory Based Solid-State Drives”.
Claim 1, Cai et al. discloses an apparatus, comprising: memory cells configured to store charges representative of stored data, the memory cells including first-type cells and second-type cells designated to store different numbers of bits in each cell [discusses memory cells storing charge and defines SLC, MLC, TLC, and QLC modes, Section II.A]; and a logic circuit coupled to the memory cells and configured to: store initial levels of charges corresponding to predetermined data at a group of the first-type cells [discloses programming cells using incremental step pulse programming to establish initial threshold voltage distribution Section II.B]; obtain a measurement output directly from the group of the first-type cells, wherein the measurement output represents charge loss from the initial levels over time [details the physics of electron leakage causing negative threshold voltage drift over time, Section IV.B]; and derive an access adjustment for reading the second-type cells based on estimating charge loss at the second-type cells using the measurement output [explains shifting the read reference voltage to locate the optimal valley between overlapping threshold distributions, Section V.A.].
Claim 2, Cai et al. discloses the apparatus of claim 1, wherein: the second-type cells are triple-level cells (TLCs); and the first-type cells are quad-level cells (QLCs) [covers both TLC and QLC engineering definitions, state counts, and reliability challenges, Section II.A].
Claim 3, Cai et al. discloses the apparatus of claim 1, wherein the second-type cells (1) have a maximum storage capacity and (2) are configured to store less than the maximum capacity to decrease write time [mentions using multi-level flash cells in the reduced bit modes, Section VI.A].
Claim 4, Cai et al. discloses the apparatus of claim 3, wherein the logic circuit is configured to determine a proxy access group that includes a set of the first type cells configured to model charge loss for the second type cells, wherein the proxy access group corresponds to a word line within group of the first-type cells used to obtain the measurement output [details that flash memory arrays are organized into physical rows sharing a common word line, Section II.A].
Claim 5, Cai et al. discloses he apparatus of claim 1, wherein the logic circuit is configured to: incrementally increase an access grouping voltage on the group of the first-type cells; determine the measurement output as the access grouping voltage that causes a predetermined reaction related to the first-type cells [Section V.B]; compute a translated measure based on the measurement output and a translation mechanism that maps measured charge losses at the first-type cells to charge loss estimations for the second-type cells; derive the access adjustment based on the translated measure; compute an adjusted access level based on combining the access adjustment with the translated measure; and read the second-type cells using the adjusted access level [Section V.B].
Claim 6, Cai et al. discloses the apparatus of claim 5, wherein the logic circuit is configured to obtain the measurement output and compute the translated measure during a reading error handling process, a media scan, a periodic scan, or a combination thereof [teaches triggering voltage adjustments reactively during a reading error handling process (Read-Retry) or proactively via background media/periodic scan (Read Scrubbing), Section V.B and VI.A].
Claim 7, Cai et al. discloses the apparatus of claim 5, wherein: the first-type cells and the second-type cells comprise a memory block, wherein the group of the first-type cells used to obtain the measurement output includes a proxy word line; wherein the first-type cells have a maximum storage density for the memory block; wherein the second-type cells are (1) connected to a separate storage word line and (2) dynamically configured for a storage density that is less than the maximum storage density; the logic circuit is further configured to: continue incrementally increasing the access grouping voltage during and after determining the measurement output and in parallel to (1) computing the translated measure, (2) deriving the (1) access adjustment, and computing the adjusted access level; reading the second-type cells based on: incrementally increasing voltage on the storage word line matching the access grouping voltage; and increasing the voltages at the storage word line at least up to the adjusted access level [Section II.A]
Claim 8, Cai et al. discloses the apparatus of claim 7, wherein: the maximum storage density for the memory block is four bits per cell; and the second-type cells are QLCs dynamically configured to store three bits or less per cell to reduce read and write times [Sections II.A and VII].
Claim 9, Cai et al. discloses the apparatus of claim 5, wherein the logic is further configured to incrementally increase the access grouping voltage based on: increasing the access grouping voltage up to a measurement minimum according to an initial step size; and increasing the access grouping voltage over and beyond the measurement minimum using a measurement step size that has a smaller magnitude, a longer sustain duration, or both in comparison to the first step size [Section V.B].
Claims 10-20 are rejected using the same rationale as Claims 1-9.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12346588. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the instant application can be found within the claims of U.S. Patent No. 12346588.
The limitations of Claims 1 and 17 are found within Claims 1 and 11 of U.S. Patent No. 12346588.
The limitations of Claim 10 are found within Claim 6 of U.S. Patent No. 12346588.
The limitations of Claims 2, 3, and 18 are found within Claims 2, 3, 12, 13, 14 of U.S. Patent No. 12346588.
The limitations of Claims 4, 5, 9, 12, 13, 16, 20 are found within Claims 6, 7, 10, 17, 20 of U.S. Patent No. 12346588.
The limitations of Claims 6, 7, 8, 14, 15, 19 are found within Claims 4, 5, 8, 9, 15, 16, 18, 19 of U.S. Patent No. 12346588.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hendrickson [US 2013/0326292]; Memories and Methods for Performing Column Repair. See par. 0003.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133
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