DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-22, 24-31, & 33-36 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Salle et al. (US 10,367,464 B2), hereinafter Salle.
Regarding claim 21, Salle discloses, in figures 2, 3, & 7, an electronic device comprising:
an antenna (202/203); and
a transceiver coupled to the antenna (Col. 4, Lines 31, “transceiver topology”…coupled to antennas 202/203), the transceiver configured to lock to a channel bandwidth to communicate signals via the antenna (Col. 6, Lines 53-59, “PLL lock/un-locking indicator circuit 395 may be triggered if the ramp up or ramp down slope of the modulation is too fast for the PLL bandwidth. In this situation, the phase error accumulates and the PLL finally unlocks. This forces the modulation to stop to avoid transmitting to an undesired (possibly forbidden) frequency”…i.e., the PLL locks to a bandwidth for communication with the antennas until an undesired slope is detected), and the transceiver comprising filter circuitry (loop filter 320) configured to change the channel bandwidth a plurality of times (Col. 6, Lines 7-10 & 37-38, “the loop of the DPLL bandwidth is changed back and forth, from low bandwidth to high bandwidth, by adapting the gain provided by gear shifting circuit 325…in other examples, the gear shifting circuit 325 may also be implemented inside the loop filter”) in alignment with respective clocking transitions and without losing the lock on the channel bandwidth (clocking transitions between the ‘fast mode’ and ‘slow mode’ indicate a change in the channel bandwidth and only unlocks in the event of a phase error accumulation).
Regarding claim 22, Salle discloses the electronic device of claim 21, and continues to disclose, in figures 2, 3, & 7, wherein the transceiver comprises:
a first portion of circuitry coupled to an output of the transceiver (681, 682, 683, 686 of the gear shift circuit of DPLL 300 may form part of the frequency generation circuit 230 and thus coupled to an output of the transceiver), the first portion of circuitry being configured to apply a gain to the signals (Col. 6, Lines 37-41, “gear shifting circuit 325 may also be implemented inside the loop filter, for example to replace a ‘proportional’ part of the loop filter 320, where the output is ‘proportional’ to the input and provides a simple gain”); and
a second portion of circuitry coupled to the output of the transceiver (650 of gear shift circuit of DPLL 300 may form part of the frequency generation circuit 230 and thus coupled to an output of the transceiver), the second portion of circuitry being configured to feedback one or more output signals to an input to the first portion of circuitry (feedback path 650 of the gear shift circuit of the DPLL 300 feeds an input 692 to the first portion of circuitry 686).
Regarding claim 24, Salle discloses the electronic device of claim 22, and continues to disclose, in figures 2, 3, & 7, wherein the filter circuitry comprises an all-digital phase locked loop that is configured to filter a signal characterized by a frequency outside of a frequency range of the channel bandwidth based on a loop bandwidth (digital phase locked loop 300 filters by a desired frequency range characterized by the loop bandwidth).
Regarding claim 25, Salle discloses the electronic device of claim 22, and continues to disclose, in figures 2, 3, & 7, wherein the filter circuitry comprises digital circuitry (digital phase locked loop 300), the transceiver being configured to transmit the signals via the antenna based on the digital circuitry amplifying at least one signal of the signals characterized by a frequency within a range of frequencies of the channel bandwidth (transmitted signal to antenna 203 from frequency generation 230 utilizing DPLL 300 generates amplified signal via multipliers 683, 680, 630 of gear-shifting block in the desired frequency range based on the loop bandwidth).
Regarding claim 26, Salle discloses the electronic device of claim 22, and continues to disclose, in figures 2, 3, & 7, wherein the digital circuitry is configured to gear shift based on receiving at least a portion of a first set of amplification data and retaining at least a portion of a second set of amplification data (Col. 9, Lines 12-16, “when transitioning from ‘slow mode’ to ‘fast mode’, the offset value 692, just before the mode change, is stored in the third flip-flop (FF3) 620. The output from third flip-flop (FF3) 620 is clocked by a first ‘fast mode’ clock trigger”…each mode is characterized by a set of amplification data), wherein the first set of amplification data is generated after the second set of amplification data (Col. 9, Lines 16-21, “Similarly, when transitioning from ‘fast mode’ to ‘slow mode’, the offset value 692, just before the mode change, is stored in the fourth flip-flop (FF4) 622. The output from fourth flip-flop (FF4) 622 is clocked by a second ‘slow mode’ clock trigger accordingly”).
Regarding claim 27, Salle discloses the electronic device of claim 22, and continues to disclose, in figures 2, 3, & 7, wherein the digital circuitry is configured to amplify the at least one signal of the signals based on digital data indicating an amount of amplification (multipliers 616, 618, 656, 658 amplify based on the gain corresponding to a mode of operation).
Regarding claim 28, Salle discloses the electronic device of claim 22, and continues to disclose, in figures 2, 3, & 7, wherein the digital circuitry comprises synchronization circuitry configured to align the at least one signal of the signals with the respective clocking transitions (Col. 9, Lines 11-21, “first circuit 610 is to update the previous value of offset that was used in the previous mode. Thus, when transitioning from ‘slow mode’ to ‘fast mode’, the offset value 692, just before the mode change, is stored in the third flip-flop (FF3) 620. The output from third flip-flop (FF3) 620 is clocked by a first ‘fast mode’ clock trigger. Similarly, when transitioning from ‘fast mode’ to ‘slow mode’, the offset value 692, just before the mode change, is stored in the fourth flip-flop (FF4) 622. The output from fourth flip-flop (FF4) 622 is clocked by a second ‘slow mode’ clock trigger accordingly.”).
Regarding claim 29, Salle discloses the electronic device of claim 22, and continues to disclose, in figures 2, 3, & 7, wherein the digital circuitry comprises a first path comprising a first multiplier configured to be loaded, at a first time, with a first amplification parameter of a plurality of amplification parameters (multipliers 656, 658 receive respective gain values of amplification parameters), and
a second path a second multiplier configured to be loaded, at a second time, with the first amplification parameter (multipliers 616, 618 receive respective gain values of amplification parameters).
Regarding claim 30, Salle discloses the electronic device of claim 22, and continues to disclose, in figures 2, 3, & 7, wherein the digital circuitry comprises an adder configured to output an output signal of a present operation based on combining an at least one amplified signal with an output signal from a previous operation (Col. 9, Lines 5-45, “610 that provides an update to adder 686 of a previous offset…new offset value is input to adder 686”), and
logic circuitry configured to feedback the output signal from the previous operation to the adder in alignment with the respective clocking transitions (Col. 9, Lines 45-49, “new offset value is input to adder 686 based on the gear-shift output signal 326 of the gear-shift circuit 600. The second circuit 650 stores the new offset by storing the output signal gs_out in first and second flip-flops (FF1) 660, and (FF2) 662”…output from adder 686 and aligned with clock transitions between modes).
Regarding claim 31, Salle discloses, in figures 2, 3, & 7, circuitry comprising:
Interfacing circuitry configured to receive a first input signal and amplification data from processing circuitry (Col. 4, Lines 13, “signal processing module 208”…interfacing circuitry for 320, 325 of frequency generation circuitry 230 receives gain values G1, G2 and an input signal via processing circuitry 208 and controller 214) and
filter circuitry configured to adjust the first input signal based on a loop bandwidth associated with the amplification data (Col. 6, Lines 7-10 & 37-38, “the loop of the DPLL bandwidth is changed back and forth, from low bandwidth to high bandwidth, by adapting the gain provided by gear shifting circuit 325…in other examples, the gear shifting circuit 325 may also be implemented inside the loop filter”…signal is adjusted based on the loop bandwidth associated with the amplification data of the associated mode of operation), the filter circuitry being operable to change the loop bandwidth a plurality of times (Col. 6, Lines 7-10 & 37-38, “the loop of the DPLL bandwidth is changed back and forth, from low bandwidth to high bandwidth, by adapting the gain provided by gear shifting circuit 325…in other examples, the gear shifting circuit 325 may also be implemented inside the loop filter”) in alignment with respective clocking transitions and without losing a lock on a channel bandwidth (clocking transitions between the ‘fast mode’ and ‘slow mode’ indicate a change in the channel bandwidth and only unlocks in the event of a phase error accumulation).
Regarding claim 33, Salle discloses the circuitry of claim 31, and continues to disclose, in figures 2, 3, & 7, wherein the filter circuitry comprises digital circuitry configured to amplify the first input signal based on the amplification data (multipliers 616, 618, 656, 658 amplify based on the gain corresponding to a mode of operation).
Regarding claim 34, Salle discloses the circuitry of claim 31, and continues to disclose, in figures 2, 3, & 7, wherein the digital circuitry is configured to receive a multi-bit number of amplification that enables the digital circuitry to perform complex loop gain changes (amplification data comprises frequency, selected gain, and offset applied to perform complex loop gain changes).
Regarding claim 35, Salle discloses the circuitry of claim 31, and continues to disclose, in figures 2, 3, & 7, wherein the filter circuitry is configured to adjust the first input signal based on the amplification data (multipliers 616, 618, 656, 658 adjust based on the gain corresponding to a mode of operation).
Regarding claim 36, Salle discloses, in figures 2, 3, & 7, a method comprising:
locking, via processing circuitry, a channel bandwidth to communicate a signal (Col. 6, Lines 53-59, “PLL lock/un-locking indicator circuit 395 may be triggered if the ramp up or ramp down slope of the modulation is too fast for the PLL bandwidth. In this situation, the phase error accumulates and the PLL finally unlocks. This forces the modulation to stop to avoid transmitting to an undesired (possibly forbidden) frequency”…i.e., the PLL locks to a bandwidth for communication with the antennas until an undesired slope is detected); and
configuring, via the processing circuitry, filter circuitry with a plurality of different loop bandwidths over time and (Col. 6, Lines 7-10 & 37-38, “the loop of the DPLL bandwidth is changed back and forth, from low bandwidth to high bandwidth, by adapting the gain provided by gear shifting circuit 325…in other examples, the gear shifting circuit 325 may also be implemented inside the loop filter”) in alignment with respective clocking transitions (clocking transitions between the ‘fast mode’ and ‘slow mode’ indicate a change in the channel bandwidth).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23 & 32 are rejected under 35 U.S.C. 103 as being unpatentable over Salle in view of Navid (US 2014/0062549 A1).
Regarding claim 23, Salle discloses the electronic device of claim 22, but fails to disclose wherein the first portion of circuitry is disposed in a proportional path of a control loop and the second portion of circuitry is disposed in an integrator path of the control loop.
However, Navid discloses, in figure 1, wherein the first portion of circuitry is disposed in a proportional path of a control loop and the second portion of circuitry is disposed in an integrator path of the control loop (Para [0017], “digital loop filter 116, output signal 104 from PD 102 is directed into a lower arm that feeds into a multiplier 110, which multiplies output signal 104 by the proportional gain constant K.sub.P. Output signal 104 is also directed into an upper arm that feeds into a multiplier 108, which multiplies output signal 104 by the integral gain constant K.sub.I. The result of this multiplication feeds into an integrator comprising an adder 112 and a unit-delay register Z.sup.-1 113”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the control loop of Navid in the device of Salle, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. [i.e., implementing second order loop control in a loop filter in a PLL] (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 32, Salle discloses the circuitry of claim 31, but fails to disclose wherein a first portion of the filter circuitry is disposed in a proportional path of a control loop and a second portion of the filter circuitry is disposed in an integrator path.
However, Navid discloses, in figure 1, wherein a first portion of the filter circuitry is disposed in a proportional path of a control loop and a second portion of the filter circuitry is disposed in an integrator path. (Para [0017], “digital loop filter 116, output signal 104 from PD 102 is directed into a lower arm that feeds into a multiplier 110, which multiplies output signal 104 by the proportional gain constant K.sub.P. Output signal 104 is also directed into an upper arm that feeds into a multiplier 108, which multiplies output signal 104 by the integral gain constant K.sub.I. The result of this multiplication feeds into an integrator comprising an adder 112 and a unit-delay register Z.sup.-1 113”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the control loop of Navid in the device of Salle, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. [i.e., implementing second order loop control in a loop filter in a PLL] (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Allowable Subject Matter
Claims 37-40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chowdhury et al. (US 2022/0303929 A1) [Figure 1. Discloses methods and apparatus for a self-synchronizing software defined radio apparatus wherein the method includes instructing, by a leader module of an RF clock module of the software defined radio apparatus and via a controller module comprising a central coordinator operative to provide a data bridge, a radio frequency (RF) transceiver to transmit a two-tone frequency signal at f.sub.1 and f.sub.2 over air, separated by a desired input clock frequency, the RF transceiver operative to receive and transmit RF signals, receiving, at a follower module, a transmitted signal, extracting, by the follower module, an envelope of the received signal, and passing the received signal through a filter to obtain a reference clock without modifying existing physical/link layer protocols.]
Josefsberg et al. (US 10,404,261 B1) [Figure 2. Discloses a RADAR unit may include a transmitter for transmitting at least one radio signal, and a receiver for receiving the at least one radio signal returned from the one or more objects. The ultra-lowphase-noisefrequency synthesizer may utilize a dual loop design comprising one main PLL and one sampling PLL, where the main PLL might include a DDS or Fractional-N PLL plus a variable divider, or the synthesizer may utilize a sampling PLL only, to reduce phase-noise from the returned radio signal. This system enhances the detection of the exact location of the vehicle based on the received RADAR signatures of objects, azimuth and distance.]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached at (571) 270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J PERENY/Examiner, Art Unit 2836
Prosecution Insights