Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The annotated version of FIG 3 of this application shows one-to-one matching of the claimed languages.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8-10 and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang, Kun-Yung Ken et al. “A 0.4-4-Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs” (cited by the applicant).
The annotated version of FIG 3 of Chang shows one-to-one matching terms, pairing exact claim language to particular language used in the prior art.
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Regarding claims 1 and 8, Chang discloses a system (FIG 1-8), and a method comprising:
a phase-locked loop (FIG 3 PLL VCO loop portion);
a phase interpolator (Phase Interpolator, in FIG 3 PLL PI loop portion); and
an interpolator control circuit (OpAmp2 with FIG 3 PLL PI loop portion),
the phase-locked loop comprising:
an oscillator (VCO) and
an oscillator control circuit (PFD, CP, CP2, Ccp, C2, OpAmpR, OpAmp1, CVCO),
the oscillator control circuit being configured to set a value (Vcp2) of an oscillator parameter to control (with OpAmp1) a frequency of oscillation of the oscillator,
the interpolator control circuit (OpAmp2 with FIG 3 PLL PI loop portion) being configured to adjust a phase interpolator parameter of the phase interpolator based on the value (Vcp2) of the oscillator parameter (Pages 748-750, section A PLL - D DCC).
Regarding claims 2 and 9, Chang discloses the system wherein the oscillator parameter is a supply voltage (Vcp2 with OpAmp1 output) of the oscillator.
Regarding claims 3 and 10, Chang discloses the system wherein the phase interpolator parameter is a supply voltage (Vcp2 with OpAmp2 output) of the phase interpolator.
Regarding claim 15, Chang discloses a system (FIG 1-8), comprising:
a voltage-controlled oscillator (VCO);
an oscillator control circuit (PFD, CP, CP2, Ccp, C2, OpAmpR, OpAmp1, CVCO);
a phase interpolator (Phase Interpolator); and
an interpolator control circuit (OpAmp2 with FIG 3 PLL PI loop portion), the voltage-controlled oscillator being configured to generate a plurality of clock phases (FIG 6 shows four phases),
the phase interpolator being configured to generate an intermediate phase from two phases of the plurality of clock phases (FIG 6),
the oscillator control circuit being configured to set a value (Vcp2) of an oscillator parameter to control a frequency of oscillation of the voltage-controlled oscillator,
the interpolator control circuit being configured to adjust a phase interpolator parameter (using OpAmp2) based on the value (Vcp2) of the oscillator parameter.
Regarding claim 16, Chang discloses the system wherein the oscillator parameter is a supply voltage (Vcp2 with OpAmp1 output) of the voltage-controlled oscillator.
Regarding claim 17, Chang discloses the system wherein the phase interpolator parameter is a supply voltage (Vcp2 with OpAmp2 output) of the phase interpolator.
Allowable Subject Matter
Claims 4-7, 11-14 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the cited references discloses nor suggests the claimed invention including “a low dropout regulator” as set forth in the claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 9,735,788) discloses a phase locked loop including a phase interpolator without mentioning a low dropout regulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah M Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH CHANG/Primary Examiner, Art Unit 2836
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