DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9 and 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brandl et al., US PG Pub 2021/0201986, in view of Acharya et al., US PGPub 2022/0043653.
With respect to claim 1, Brandl teaches an electronic device comprising:
a semiconductor chip, comprising an input/output (I/O) interface circuit (par. 46, the memory controller 500 and associated physical interface PHY. Par. 16 discloses that the invention is directed towards a SOC (system-on-chip), a semiconductor chip); and
an integrated circuit (IC), external to the semiconductor chip, wherein the IC comprises: a first memory device, external to the semiconductor chip (pars. 60-62 and fig. 8, the non-volatile memory module 830, the non-volatile memory module 830 external to the memory controller);
wherein the semiconductor chip communicates with the first memory device via the I/O interface circuit (pars. 58-60, the memory controller communicates with the memory module via interface PHY);
Brandl fails to teach that the first memory device is an internal volatile memory of the IC. Acharya teaches:
a first memory device, being an internal volatile memory of the IC and external to the semiconductor chip (pars. 26-27, the local memory module 222 is internal to the GPU 202, the IC of the claim. The external memory module 224 is the semiconductor chip external to the IC)
the semiconductor chip is arranged to store at least one hardware setting of the semiconductor chip into the first memory device before a power-off event of the semiconductor chip; and after the power-off event of the semiconductor chip, separate chips, including the semiconductor chip and the IC, both enter a power saving mode, and the first memory device of the IC that is an off-chip memory device of the semiconductor chip is powered during a period in which the at least one hardware setting of the semiconductor chip is stored in the first memory device of the IC that is operating in the power saving mode (par. 27, the hardware states of the saved registers are stored in the on-chip local memory 222, the hardware states corresponding to the hardware settings of the claim, and after the power-off event, the on-chip local memory 222 in the always-on power domain stays powered, while the power-collapsible domains and the external memory are powered-off, meaning the GPU 202 and external memory module are in power saving mode).
It would have been obvious to one of ordinary skill in the art, having the teachings of Brandl and Acharya before him before the earliest effective filing date, to modify the memory storage system of Brandl with the memory storage system of Acharya, in order to save the hardware settings to an external memory, as it is important to ensure that the data is retained even in the case of a power collapse in another domain, as taught by Acharya in pars. 41-42.
With respect to claim 2, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, wherein the IC is a power management integrated circuit (PMIC) of the electronic device (par. 16, the DRAMs perform power management).
With respect to claim 3, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, wherein the I/O interface circuit comprises: general-purpose input/output (GPIO) hardware (par. 60, the memory module I/O signals are in accordance with the DDR4 Specification, which may be considered general purpose I/O); and a GPIO latch circuit, arranged to latch status of the GPIO hardware (par. 60, the latch); the IC is arranged to enable the GPIO latch circuit before the power-off event of the semiconductor chip (pars. 60-61, the latch is enabled before entering a lower power state).
With respect to claim 4, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, wherein the I/O interface circuit comprises general-purpose input/output (GPIO) hardware (par. 60, the memory module I/O signals are in accordance with the DDR4 Specification, which may be considered general purpose I/O); and the IC is arranged to make the GPIO hardware enter an isolation state before the power-off event of the semiconductor chip, to prevent unexpected unknown signal from a power-off domain causing GPIO leakage (par. 75, the DRAMs are set into self-refresh mode).
With respect to claim 5, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, further comprising: a second memory device, external to the semiconductor chip (par. 32, memory channel 340); wherein the semiconductor chip further comprises: a memory controller circuit, arranged to control access of the second memory device, wherein the memory controller circuit is further arranged to instruct the second memory device to enter a self-refresh mode before the power-off event of the semiconductor chip (par. 47, where the controller controls both memory channel 330 and 340, and pars. 74-75, which discussed putting memory into self-refresh mode and power off).
With respect to claim 6, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, further comprising: a second memory device, external to the semiconductor chip; wherein the semiconductor chip further comprises: a memory controller circuit, arranged to control access of the second memory device; and the IC is further arranged to make the second memory device enter an isolation state before the power-off event of the semiconductor chip (par. 75, the DRAMs are set into self-refresh mode).
With respect to claim 7, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, further comprising: a second memory device, external to the semiconductor chip (par. 32, memory channel 340); wherein the semiconductor chip further comprises: a memory controller circuit, arranged to control access of the second memory device according to memory parameters of the second memory device, where said at least one hardware setting comprises the memory parameters of the second memory device (pars. 74-75, the PHY settings).
With respect to claim 8, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, wherein said at least one hardware setting comprises general-purpose input/output (GPIO) pinmux parameters of the I/O interface circuit (par. 53, the DRAM timing parameters).
With respect to claim 9, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 1, further comprising: a second memory device, external to the semiconductor chip (par. 32, memory channel 340); wherein the semiconductor chip further comprises: a modulator/demodulator (modem) circuit (par. 20, the wireless local area network card for transmission and reception of signals); and a memory controller circuit, arranged to control access of the second memory device (par. 47, the memory channel controller 624); the semiconductor chip is further arranged to store a hardware setting of the modem circuit into the second memory device via the memory controller circuit before the power-off event of the semiconductor chip(pars. 74-75 and the associated fig. 10, storing settings into a non-volatile location in step 101, before powering down in step 1025).
With respect to claim 11, Brandl teaches an electronic device comprising:
a semiconductor chip, comprising an input/output (I/O) interface circuit (par. 46, the memory controller 500 and associated physical interface PHY. Par. 16 discloses that the invention is directed towards a SOC (system-on-chip), a semiconductor chip); and
an integrated circuit (IC), external to the semiconductor chip, wherein the IC comprises: a first memory device, external to the semiconductor chip (pars. 60-62 and fig. 8, the non-volatile memory module 830, the non-volatile memory module 830 external to the memory controller);
wherein the semiconductor chip communicates with the first memory device via the I/O interface circuit (pars. 58-60, the memory controller communicates with the memory module via interface PHY); and
Brandl fails to teach that the first memory device is an internal volatile memory of the IC. Acharya teaches:
a first memory device, being an internal volatile memory of the IC and external to the semiconductor chip (pars. 26-27, the local memory module 222 is internal to the GPU 202, the IC of the claim. The external memory module 224 is the semiconductor chip external to the IC)
the semiconductor chip is arranged to fetch at least one hardware setting of the semiconductor chip from the first memory device after a power-on event of the semiconductor chip; and before the power-on event of the semiconductor chip, separate chips, including the semiconductor chip and the IC that is an off-chip memory device of the semiconductor chip is powered during a period in which the at least one hardware setting of the semiconductor chip is stored in the first memory device of the IC that is operating in a power saving mode, and the IC leaves the power saving mode. (par. 27, the state data corresponds to the hardware settings of the claim, and after detecting the power-on event, the state data is restored from on-chip local memory 222).
It would have been obvious to one of ordinary skill in the art, having the teachings of Brandl and Acharya before him before the earliest effective filing date, to modify the memory storage system of Brandl with the memory storage system of Acharya, in order to save the hardware settings to an external memory, as it is important to ensure that the data is retained even in the case of a power collapse in another domain, as taught by Acharya in pars. 41-42.
With respect to claim 12, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, wherein the first memory device is an internal memory of an integrated circuit (IC) of the electronic device (par. 16, the DRAMs perform power management).
With respect to claim 13, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, wherein the I/O interface circuit comprises: general-purpose input/output (GPIO) hardware (par. 60, the memory module I/O signals are in accordance with the DDR4 Specification, which may be considered general purpose I/O); and a GPIO latch circuit, arranged to latch status of the GPIO hardware (par. 60, the latch); the IC is arranged to disable the GPIO latch circuit before the power-on event of the semiconductor chip (par. 62, exiting low power mode).
With respect to claim 14, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, wherein the I/O interface circuit comprises general-purpose input/output (GPIO) hardware (par. 60, the memory module I/O signals are in accordance with the DDR4 Specification, which may be considered general purpose I/O); and the IC is arranged to make the GPIO hardware leave an isolation state before the power-on event of the semiconductor chip (par. 76, exit self-refresh mode).
With respect to claim 15, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, further comprising: a second memory device, external to the semiconductor chip (par. 32, memory channel 340); wherein the semiconductor chip further comprises: a memory controller circuit, arranged to control access of the second memory device, wherein the memory controller circuit is further arranged to instruct the second memory device to leave a self-refresh mode after the power-on event of the semiconductor chip par. 47, where the controller controls both memory channel 330 and 340, and par 76, exiting self-refresh mode).
With respect to claim 16, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, further comprising: a second memory device, external to the semiconductor chip; wherein the semiconductor chip further comprises: a memory controller circuit, arranged to control access of the second memory device; and the IC is further arranged to make the second memory device leaves an isolation state after the power-on event of the semiconductor chip (par. 76, exiting self-refresh mode).
With respect to claim 17, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, further comprising: a second memory device, external to the semiconductor chip (par. 32, memory channel 340); wherein the semiconductor chip further comprises: a memory controller circuit, arranged to control access of the second memory device according to memory parameters of the second memory device, where said at least one hardware setting comprises the memory parameters of the second memory device (pars. 74-75, the PHY settings).
With respect to claim 18, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, wherein said at least one hardware setting comprises general-purpose input/output (GPIO) pinmux parameters of the I/O interface circuit (par. 53, the DRAM timing parameters).
With respect to claim 19, Brandl and Acharya teach the limitations of the parent claim. Brandl further teaches the electronic device of claim 11, further comprising: a second memory device, external to the semiconductor chip (par. 32, memory channel 340); wherein the semiconductor chip further comprises: a modulator/demodulator (modem) circuit (par. 20, the wireless local area network card for transmission and reception of signals); and a memory controller circuit, arranged to control access of the second memory device (par. 47, the memory channel controller 624); the semiconductor chip is further arranged to load a hardware setting of the modem circuit from the second memory device via the memory controller circuit after the power-on event of the semiconductor chip (par. 76, restoring the PHY settings).
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 10, no prior art of record teaches “after receiving a command from a host application processor for activation of a fast boot mode, a modulator/demodulator (modem) circuit of the semiconductor chip prepares to go to an idle mode, and instructs a microcontroller unit (MCU) of the semiconductor chip to go to the fast boot mode; in response to instruction from the modem circuit, the MCU stores a backup of memory parameters of a second memory device, external to the semiconductor chip, into the first memory device of the IC, and instructs a secure system power manager (SSPM) and a system power manager (SPM) of the semiconductor chip to go to the fast boot mode; in response to instruction from the MCU, the SSPM stores a backup of general-purpose input/output (GPIO) pinmux parameters of the I/O interface circuit into the first memory device of the IC, and enters an idle mode; in response to instruction from the MCU, the SPM sends a command to a memory controller of the semiconductor chip for instructing the second memory device to leave a normal mode and enter a self-refresh mode, instructs the IC to isolate the second memory device after the second memory device enters the self-refresh mode, and instructs the IC to enter the power saving mode after the second memory device is isolated; and in response to instruction from the SPM, the IC makes GPIO hardware of the I/O interface circuit enter an isolation state, triggers the power-off event of the semiconductor chip, and enters the power saving mode,” in combination with all of the limitations of the parent claim.
With respect to claim 20, no prior art of record teaches “after receiving a command from a host application processor, the IC exits the power saving mode, makes general-purpose input/output (GPIO) hardware of the I/O interface circuit leave an isolation state, and triggers the power-on event of the semiconductor chip such that a boot sequence of the semiconductor chip is started; and after the boot sequence of the semiconductor chip is started, a microcontroller unit (MCU) of the semiconductor chip fetches GPIO pinmux parameters from the first memory device of the IC, and refers to the fetched GPIO pinmux parameters to restore state of the GPIO hardware; fetches memory parameters of a second memory device external to the semiconductor chip from the first memory device of the IC, and refer to the fetched memory parameters to configure a memory controller of the semiconductor chip; instructs the IC to make the second memory device leave an isolation state; and sends a command to the memory controller such that the memory controller instructs the second memory device to leave a self-refresh mode and re-enter a normal mode,” in combination with all of the limitations of the parent claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huang, US PGPub 2012/0239918 teaches a fast boot mode and a sleeping state. Yu et al., US PGPub 2007/0028084 teaches a fast boot mode and a partial power-down.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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