Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendments and Arguments
Amendments and arguments filed on 07/24/2026 have been fully considered and are not found to place the application in a condition for allowance. Specifically, the applicant asserts that because “a part of the threshold voltage” is compensated for, “the driving current is still affected by the non-compensated part of the threshold voltage of the driving transistor T1.” However, note that ¶ 107 of Lee discloses that “the driving current may include the data voltage component and the threshold voltage component having a value smaller than the threshold voltage. In other words, a part of the threshold voltage of the driving transistor T1 may be compensated for.” Lee specifies the “threshold voltage component” to be ((2*C_C1)/(C_C1+C_C3))*VTH. As noted by the applicant the current value of the transistor is determined by Vgs-Vth. Accordingly, it is clear, based on Lee’s teachings, that by setting C1 and C3 to have similar values, the entirety of the VTH component will be compensated. In other words, Lee recognizes that C1 and C3 may not be manufactured to be exactly equal and therefore it is disclosed that the driving current may include a threshold voltage component. However, the objective of Lee is to fully compensate for the threshold voltage as it is evident from ¶ 79 and ¶ 91: “Since the gate-source voltage of the driving transistor T1 includes a data voltage component and a threshold voltage component, the driving current may include the data voltage component without including the threshold voltage component. In other words, the threshold voltage of the driving transistor T1 may be compensated for”. Accordingly, the amended limitations are found to be obvious in view of the teachings of Lee in view of Kim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2024/0274079 A1, hereinafter “Lee”, in view of Kim et al., US 2025/0201174 A1, hereinafter “Kim”.
Regarding claim 1, Lee teaches a pixel circuit (fig. 11, ¶ 96), comprising: a light-emitting diode (EE); a first-first internal-node setting transistor (T3), electrically connected to other terminal of the light-emitting diode and a first internal-node (N2); a first-second internal-node setting transistor (T2), electrically connected to a second internal-node (N1) and a data-line (VDATA), wherein during a pixel-data voltage-setting duration, a voltage of the data-line is equivalent to a pixel-data setting voltage, and the first-second internal-node setting transistor conducts the pixel-data voltage to the second internal-node (fig. 14, ¶ 104-106); and a light-intensity control transistor (T1), electrically connected to the first internal-node, the second internal-node, and a ground voltage line (see connection to nodes N1-N3, note that N3 is connected to ELVSS through EE), wherein a voltage of the supply voltage line (ELVDD) is greater than a voltage of the ground voltage line (¶ 70: ELVDD is high power; ¶ 71: ELVSS is low power), wherein during a pixel light-emission duration after the pixel-data voltage-setting duration ends (fig. 12, P3, also see fig. 15), the light-intensity control transistor is switched on by a voltage of the second internal-node, as being related to the voltage of the supply voltage line and a voltage difference between the pixel-data setting voltage and a threshold voltage of the light-intensity control transistor (¶ 107), and a current value of a pixel current flowing from the supply voltage line to the ground voltage line, through the light-emitting diode, the first-first internal-node setting transistor, the first internal-node, and the light-intensity control transistor is related to the pixel-data setting voltage but not the threshold voltage of the light-intensity control transistor (fig. 12, P3, also see fig. 16; ¶ 106-107, see N1 and N2 voltages; note that setting C1 and C3 to be of similar values meets such a requirement according to ((2*C_C1)/(C_C1+C_C3))*VTH which would simply yield VTH which is then canceled out by the threshold voltage of the transistor).
Lee does not specifically teach a light-emitting diode, having a terminal being electrically connected to a supply voltage line.
Kim, however, clearly teaches a light-emitting diode (fig. 3, LED), having a terminal being electrically connected to a supply voltage line (VDD).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Lee in view of Kim. The references teach pixel circuits and while Lee teaches a pixel circuit having a common cathode configuration, Kim teaches that pixel circuits may be configured as common cathode or common anode (see fig. 2 and fig. 3). Accordingly, one would have been motivated to simply change the LED configuration from common cathode to common anode while expecting the same result of driving the LED device.
Regarding claim 2, Lee teaches that the first-first internal-node setting transistor is electrically connected to a light-emission activate gate-line (fig. 11, EM1), wherein the first-first internal-node setting transistor is switched on in response to a voltage of the light-emission activate gate-line during the pixel light-emission duration (fig. 12, P3, see EM1 which is switched on according to VL voltage, ¶ 73), and the first-second internal-node setting transistor is electrically connected to a pixel-data setting gate-line (GW), wherein the first-second internal-node setting transistor is switched on in response to a voltage of the pixel-data setting gate-line during the pixel-data voltage-setting duration (fig. 12, see GW activation during P2).
Regarding claim 3, Lee teaches a second-first internal-node setting transistor (fig. 11, T5), electrically connected to a reset gate-line (GB), wherein the second-first internal-node setting transistor is switched on in response to a voltage of the reset gate-line during a light-intensity reset duration before the pixel-data voltage-setting duration starts (fig. 12, P1, ¶ 103); a second-second internal-node setting transistor (fig. 11, T4), electrically connected to the second internal-node (N1), wherein the second-second internal-node setting transistor is switched on in response to the voltage of the reset gate-line during the light-intensity reset duration (fig. 12, P1, ¶ 103); and a third-second internal-node setting transistor (fig. 11, T6), electrically connected to the second internal-node (N1), a third internal-node (N4), and the light-emission activate gate-line (EM1), wherein the third-second internal-node setting transistor is switched on in response to the voltage of the light-emission activate gate-line during the pixel light-emission duration (fig. 12, see P3, ¶ 107).
Lee does not teach that the second-second internal-node setting transistor is connected to the reset gate line.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Lee to connect the second-second internal-node setting transistor to the same reset gate line (combine GI and GB). As disclosed in figs. 2-5 GB and GI carry identical signals. Furthermore, note that the operation of the circuit of fig. 11 as shown in fig. 12 and disclosed in ¶ 106 during P2 does not rely on the VAINT voltage. In other words, during P2 GB may be set to VH voltage at which point GI and GB of fig. 12 would have identical signals similar to the teachings of figs. 2-5. Accordingly, it would have been obvious to connect T4 and T5 to the same reset gate line thereby reducing the number of gate lines and simplifying the circuit.
Regarding claim 4, Lee teaches that the second-first internal-node setting transistor and the second-second internal-node setting transistor are electrically connected to one of the supply voltage line and a preset voltage line (fig. 11, T4 and T5 connection to VINT which per ¶ 72 is equal to VAINT and may be equal to ELVSS).
Regarding claim 5, Lee does not specifically teach that the voltage of the supply voltage line is equivalent to a voltage of the preset voltage line.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Lee in order to set the voltage of the supply voltage line equivalent to a voltage of the preset voltage line. Note that the LED of Lee is a common cathode configuration wherein the supply voltage connected to the LED is ELVSS. Lee teaches in ¶ 72 that the preset voltage lines are equivalent to ELVSS. Lee in view of Kim, as applied above, teaches that the supply voltage connected to the LED may be ELVDD. Accordingly, it would have been obvious to set ELVDD equivalent to a voltage of the preset voltage line because both ELVDD and ELVSS are known constant values according to which one would have configured the pixel circuit, expecting the same result of driving the pixel circuit while compensating for the threshold voltage.
Regarding claim 6, Lee teaches a capacitor (fig. 11, C1), electrically connected to the first internal-node (N2) and the third internal-node (N4); a first-third internal-node setting transistor (T7), electrically connected to the pixel-data setting gate-line (GW), wherein the first-third internal-node setting transistor is switched on in response to the voltage of the pixel-data setting gate-line during the pixel-data voltage-setting duration (fig. 12, P2, ¶ 106).
Lee does not teach a second-third internal-node setting transistor, electrically connected to the reset gate-line and the third internal-node, wherein the second-third internal-node setting transistor is switched on in response to the voltage of the reset gate-line during the light-intensity reset duration.
Kim teaches a second-third internal-node setting transistor (fig. 6, T6), electrically connected to the reset gate-line (SC2) and the third internal-node (N2), wherein the second-third internal-node setting transistor is switched on in response to the voltage of the reset gate-line during the light-intensity reset duration (fig. 7, see SC2, ¶ 116-117).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Lee in view of Kim. The references teach pixel circuits and Kim further teaches a similar storage capacitor. Kim further teaches that during the reset period, both electrodes of the capacitor are initialized or reset. One would have been motivated to make such a combination because Kim clearly teaches that such a configuration improves the luminance uniformity of the pixels (¶ 117).
Regarding claim 7, Lee teaches that the first-third internal-node setting transistor is electrically connected to one of the ground voltage line, the supply voltage line, and a preset voltage line (see fig. 11, T7).
Lee does not teach that the second-third internal-node setting transistor is electrically connected to one of the ground voltage line, the supply voltage line, and the preset voltage line.
Kim teaches that the second-third internal-node setting transistor is electrically connected to one of the ground voltage line, the supply voltage line, and the preset voltage line (fig. 6, T6 connected to VDATA lines which provides a preset voltage).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Lee in view of Kim. The references teach pixel circuits and Kim further teaches a similar storage capacitor. Kim further teaches that during the reset period, both electrodes of the capacitor are initialized or reset. One would have been motivated to make such a combination because Kim clearly teaches that such a configuration improves the luminance uniformity of the pixels (¶ 117).
Regarding claim 8, Lee teaches a capacitor (fig. 11, C1), electrically connected to the first internal-node and a third internal-node (see fig. 11); and a control-combined transistor (T7), electrically connected to the third internal-node (N4) and a control-combined gate-line (GW), wherein the control-combined transistor is switched on in response to a voltage of the control-combined gate-line during the pixel-data voltage-setting duration (fig. 12, see P2, ¶ 106).
Lee does not teach that the control-combined transistor is switched on in response to a voltage of the control-combined gate-line during the light-intensity reset duration and the pixel-data voltage-setting duration.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Lee in order to turn on T7 during P1 and P2. Note that such a configuration may be achieved by simply controlling T7 via the GB line instead of the GW line. Such a modification would have been obvious to one of ordinary skill because as noted in ¶ 103, during the P1 period, the voltage of N4 is not relevant to the operation of the circuit and T6 is off. In other words, turning on T7 during P1 does not change the operation of the circuit. Accordingly, one would have been motivated to make such a modification expecting the same result of driving the pixel circuit while compensating for the threshold voltage of the driving transistor.
Regarding claim 9, Lee teaches that the control-combined transistor is electrically connected to one of the ground voltage line, the supply voltage line, and a preset voltage line (fig. 11, see T7 connection to ELVDD).
Regarding claim 10, Lee teaches that the voltage of the reset gate-line is equivalent to a low gate-control voltage during the light-intensity reset duration (fig. 12, see GI level at P1), and the voltage of the reset gate-line is equivalent to a high gate-control voltage during the pixel-data voltage-setting duration and the pixel light-emission duration (fig. 12, see GI level at P2 and P3); the voltage of the pixel-data setting gate-line is equivalent to the low gate-control voltage during the pixel-data voltage-setting duration (fig. 12, see GW at P2), and the voltage of the pixel-data setting gate-line is equivalent to the high gate-control voltage during the light-intensity reset duration and the pixel light-emission duration (fig. 12, see GW at P1 and P3); and the voltage of the light-emission activate gate-line is equivalent to the low gate-control voltage during the pixel light-emission duration (fig. 12, see EM1 at P3), and the voltage of the light-emission activate gate-line is equivalent to the high gate-control voltage during the light-intensity reset duration and the pixel-data voltage-setting duration (fig. 12, see EM1 at P1 and P2).
Regarding claim 11, Lee teaches that the pixel-data setting voltage corresponds to a grayscale of the pixel circuit (¶ 67, data voltages VDATA correspond to grayscales of the pixels), and a timing control circuit (fig. 1, elements 200 and 400) sets the voltage of the data-line to be equivalent to the pixel-data setting voltage before the pixel-data voltage-setting duration starts (¶ 60-61, 64 and 67 wherein the voltage of the data line is set and then converted to analog signals before being provided to the pixels during P2).
Regarding claim 12, Lee teaches that the light-emitting diode emits light during the pixel light-emission duration, and light-intensity of the light is determined by the pixel current (¶ 107).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621
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