Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated Janakiraman et al. (US Patent Number 8,766,839).
Regarding claim 1, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2) comprising: a digital-to-analog conversion circuit (150, fig. 1) configured to receive an analog input signal during a sampling period and receive a first set of reference signals according to a first set of switch control signals during a holding period so as to accomplish charge redistribution and thereby output a sampling-and-switching operation result, the digital-to-analog conversion circuit including: a first set of switches configured to determine a coupling state of each capacitor of a first capacitor group according to the first set of switch control signals, wherein the first set of reference signals received by the digital-to-analog conversion circuit varies with a change in the first set of switch control signals (figs. 1, 2; col. 2, line 35 to col. 3, line 59) and the first capacitor group configured to sample the analog input signal during the sampling period and receive the first set of reference signals through the first set of switches during the holding period so as to accomplish the charge redistribution, the first capacitor group including: a first subsidiary capacitor group, wherein each capacitor of the first subsidiary capacitor group is composed of one or more first unit capacitor(s) (figs. 1, 2; col. 2, line 35 to col. 3, line 59) and a second subsidiary capacitor group, wherein each capacitor of the second subsidiary capacitor group is composed of one or more second unit capacitor(s), a layout of the second unit capacitor is different from a layout of the first unit capacitor, and a designed capacitance value of the second unit capacitor is greater than a designed capacitance value of the first unit capacitor (figs. 1, 2; col. 2, line 35 to col. 3, line 59); a comparison circuit configured to generate a comparison result (170, fig. 1) according to the sampling- and-switching operation result; and a control circuit (190, fig. 1) configured to generate the first set of switch control signals and a digital output signal according to the comparison result.
Regarding claim 13, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2) comprising a first set of switches and a first capacitor group (fig. 2) , wherein: the first capacitor group is configured to receive an analog input signal during a sampling period and then receive a first set of reference signals through the first set of switches during a holding period so as to accomplish charge redistribution and thereby output a sampling-and-switching operation result, the first capacitor group including: a first subsidiary capacitor group, wherein each capacitor of the first subsidiary capacitor group is composed of one or more first unit capacitor(s) (figs. 1, 2; col. 2, line 35 to col. 3, line 59); and a second subsidiary capacitor group, wherein each capacitor of the second subsidiary capacitor group is composed of one or more second unit capacitor(s), a layout of the second unit capacitor is different from a layout of the first unit capacitor, and a designed capacitance value of the second unit capacitor is greater than a designed capacitance value of the first unit capacitor (figs. 1, 2; col. 2, line 35 to col. 3, line 59);
Regarding claim 2, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2) wherein the first unit capacitor has a minimum capacitance value among all capacitors of the first subsidiary capacitor group and the second unit capacitor has a minimum capacitance value among all capacitors of the second subsidiary capacitor group (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 3, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein the designed capacitance value of the second unit capacitor is greater than twice the designed capacitance value of the first unit capacitor (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 4, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2)wherein: the first subsidiary capacitor group includes a first capacitor and a second capacitor, the first capacitor is composed of P first unit capacitor(s), the second capacitor is composed of Q first unit capacitor(s), the P and the Q are positive integers, and the P is different from the Q; and the second subsidiary capacitor group includes a third capacitor and a fourth capacitor, the third capacitor is composed of X second unit capacitor(s), the fourth capacitor is composed of Y second unit capacitor(s), the X and the Y are positive integers, and the X is different from the Y (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 5, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein the designed capacitance value of the second unit capacitor is greater than a designed capacitance value of any capacitor of the first subsidiary capacitor group (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 6, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein an adjusted capacitance value of the first unit capacitor is equal to a product of a measured capacitance value of the first unit capacitor and a first coefficient, a ratio of the adjusted capacitance value of the first unit capacitor to a measured capacitance value of the second unit capacitor meets a predetermined ratio, and the control circuit determines the digital output signal according to the first coefficient (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 7, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein when a single change in the first set of switch control signals changes a coupling state of M first unit capacitor(s) of the first subsidiary capacitor group during the holding period, the control circuit adjusts a digital code corresponding to the M according to the first coefficient and thereby generates a part of the digital output signal, in which the M is a positive integer not greater than a number of all first unit capacitor(s) of the first subsidiary capacitor group (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 8, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein the control circuit (190, fig. 1) includes: a control-logic circuit configured to generate the first set of switch control signals according to the comparison result and generate the digital code corresponding to the M;a digital code weight assignment circuit configured to assign the first coefficient appropriate for the digital code; and a digital code adjustment circuit configured to adjust the digital code according to the first coefficient (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 9, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein an adjusted capacitance value of the second unit capacitor is equal to a product of a measured capacitance value of the second unit capacitor and a second coefficient, a ratio of the adjusted capacitance value of the second unit capacitor to a measured capacitance value of the first unit capacitor meets a predetermined ratio, and the control circuit determines the digital output signal according to the second coefficient (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 10, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2),, wherein when a single change in the first set of switch control signals changes a coupling state of N second unit capacitor(s) of the second subsidiary capacitor group during the holding period, the control circuit adjusts a digital code corresponding to the N according to the second coefficient and thereby generates a part of the digital output signal, in which the N is a positive integer not greater than a number of all second unit capacitor(s) of the second subsidiary capacitor group (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 11, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein the control circuit (190, fig. 1) includes: a control-logic circuit configured to generate the first set of switch control signals according to the comparison result and generate the digital code corresponding to the N; a digital code weight assignment circuit configured to assign the second coefficient appropriate for the digital code; and a digital code adjustment circuit configured to adjust the digital code according to the second coefficient (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 12, Jankirman et al. disclose a successive approximation register analog-to-digital converter (SAR ADC) (figs. 1, 2), wherein the analog input signal is a differential signal composed of a noninverting signal and an inverting signal, the first capacitor group is configured to sample the noninverting signal during the sampling period, the analog-to-digital conversion circuit further includes a second capacitor group configured to sample the inverting signal during the sampling period (figs. 1, 2; col. 2, line 35 to col. 3, line 59)., and the second capacitor group includes:a third subsidiary capacitor group, wherein each capacitor of the third subsidiary capacitor group includes one or more third unit capacitor(s), (figs. 1, 2; col. 2, line 35 to col. 3, line 59) and the third unit capacitor is equivalent to the first unit capacitor; and a fourth subsidiary capacitor group, wherein each capacitor of the fourth subsidiary capacitor group includes one or more fourth unit capacitor(s), and the fourth unit capacitor is equivalent to the second unit capacitor (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 14, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2), wherein the first unit capacitor has a minimum capacitance value among all capacitors of the first subsidiary capacitor group and the second unit capacitor has a minimum capacitance value among all capacitors of the second subsidiary capacitor group (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 15, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2), wherein the designed capacitance value of the second unit capacitor is greater than twice the designed capacitance value of the first unit capacitor (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 16, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2) wherein: the first subsidiary capacitor group includes a first capacitor and a second capacitor, the first capacitor is composed of P first unit capacitor(s), the second capacitor is composed of Q first unit capacitor(s), the P and the Q are positive integers, and the P is different from the Q; and the second subsidiary capacitor group includes a third capacitor and a fourth capacitor, the third capacitor is composed of X second unit capacitor(s), the fourth capacitor is composed of Y second unit capacitor(s), the X and the Y are positive integers, and the X is different from the Y (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 17, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2), wherein the designed capacitance value of the second unit capacitor is greater than a designed capacitance value of any capacitor of the first subsidiary capacitor group (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 18, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2) wherein an adjusted capacitance value of the first unit capacitor is equal to a product of a measured capacitance value of the first unit capacitor and a first coefficient, a ratio of the adjusted capacitance value of the first unit capacitor to a measured capacitance value of the second unit capacitor meets a predetermined ratio, and the control circuit determines the digital output signal according to the first coefficient (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 19, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2), wherein an adjusted capacitance value of the second unit capacitor is equal to a product of a measured capacitance value of the second unit capacitor and a second coefficient, a ratio of the adjusted capacitance value of the second unit capacitor to a measured capacitance value of the first unit capacitor meets a predetermined ratio, and the control circuit determines the digital output signal according to the second coefficient (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Regarding claim 20, Jankirman et al. disclose a digital-to-analog conversion circuit (fig. 1, 2), wherein the analog input signal is a differential signal composed of a noninverting signal and an inverting signal, the first capacitor group is configured to sample the noninverting signal during the sampling period, the analog-to-digital conversion circuit further includes a second capacitor group configured to sample the inverting signal during the sampling period, and the second capacitor group includes: a third subsidiary capacitor group, wherein each capacitor of the third subsidiary capacitor group includes one or more third unit capacitor(s), and the third unit capacitor is equivalent to the first unit capacitor; and a fourth subsidiary capacitor group, wherein each capacitor of the fourth subsidiary capacitor group includes one or more fourth unit capacitor(s), and the fourth unit capacitor is equivalent to the second unit capacitor (figs. 1, 2; col. 2, line 35 to col. 3, line 59).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEAN BRUNER JEANGLAUDE whose telephone number is (571)272-1804. The examiner can normally be reached Monday-Thursday 7:00 AM-5:00 PM.
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845
