DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application, 18/349389 filed on 07/10/2023, under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. US12,353,757. Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons shown below.
Instant Application 19/241123
US Patent 12,353,757
Claim 13. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller comprises
a controller memory buffer (CMB) allocated to a host device for use by the host device, and wherein the controller is configured to:
determine whether a portion of the CMB can be used by the controller based on a usage pattern of the CMB by the host device, wherein the usage pattern is determined based on analyzing a number of past workloads of the CMB and a current workload of the CMB; and
utilize the portion of the CMB to store non-host data based on the determining, wherein the portion of the CMB remains allocated to the host device.
Claim 1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller comprises:
a volatile memory device, wherein the volatile memory device comprises a controller memory buffer (CMB),
wherein the CMB is allocated to a host device for use by the host device; and
a CMB allocation module, wherein the CMB allocation module is configured to:
analyze a usage pattern of the CMB, wherein analyzing the usage pattern of the CMB comprises analyzing a number of past workloads of the CMB and a current workload of the CMB;
determine whether a portion of the CMB can be used by the controller based on the usage pattern; and
notify the controller of the portion of the CMB that can be used by the controller based on the determining; and
wherein the controller is configured to:
utilize the portion of the CMB for management data, responsive to the notifying, wherein the portion of the CMB remains allocated to the host device.
The limitations recited in claim 13 of instant application are substantially similar as the limitations recited in claim 1 of US Patent 12,353,757. Claim 1 of the US patent includes additional limitations such as “wherein the volatile memory device comprises a controller memory buffer (CMB)”; “ notify the controller of the portion of the CMB that can be used by the controller based on the determining”; and “utilize the portion of the CMB for management data, responsive to the notifying, wherein the portion of the CMB remains allocated to the host device”. It would have been obvious to a person having ordinary skill in the art that a continuation/child application may broaden the scope of claims by removing some limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US2019/0065102), hereinafter Shin in view of Bolkhovitin et al. (US 2018/0341606), hereinafter Bolkhovitin, and further in view of Holmes (US10, 942,866), hereinafter Holmes and Benisty (US2021/0232338), hereinafter Benisty.
Regarding claim 13, Shin teaches a data storage device, comprising:
a memory device (Shin, Fig.1, memory device 1100); and
a controller (Shin, Fig.1, memory controller 1200) coupled to the memory device (Shin, Fig.1), wherein the controller comprises a controller memory buffer (CMB) (Shin, [0034], the memory controller 1200 may include a processor 710, a memory buffer 720; [0058], the memory buffer 720 may include a controller memory buffer 721) allocated to a host device for use by the host device (Shin, [0059], The controller memory buffer 721 is a memory space allocated for the host 2000, and is a memory space accessible by the host 2000), and wherein the controller is configured to:
determine whether a portion of the CMB can be used by the controller based on a usage pattern of the CMB by the host device, wherein the usage pattern is determined based on analyzing a number of past workloads of the CMB and a current workload of the CMB; and
utilize the portion of the CMB (Shin,[0060], the controller memory buffer 721 may be a space shared by the host 2000 and the memory system 1000) to store non-host data based on the determining, wherein the portion of the CMB remains allocated to the host device (Shin, [0059], The controller memory buffer 721 is a memory space allocated for the host 2000).
Shin does not explicitly teach determine whether a portion of the CMB can be used by the controller based on a usage pattern of the CMB by the host device, wherein the usage pattern is determined based on analyzing a number of past workloads of the CMB and a current workload of the CMB; utilize the portion of the CMB to store non-host data based on the determining, as claimed.
However, Shin in view of Bolkhovitin teaches utilize the portion of the CMB to store non-host data (Bolkhovitin, [0117], the mapping tables are stored/located in the storage devices, with portions stored in CMBs of the main controller subsystem for fast access), wherein the portion of the CMB remains allocated to the host device (Shin, [0059]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shin to incorporate teachings of Bolkhovitin to store portions of storage address mapping tables in one or more controller memory buffers. A person of ordinary skill in the art would have been motivated to combine the teachings of Shin with Bolkhovitin because it improves performance of the storage system disclosed in Shin by providing fast access to mapping tables associated with the storage system (Bolkhovitin, [0117]).
The combination of Shin does not explicitly teach determine whether a portion of the CMB can be used by the controller based on a usage pattern of the CMB by the host device, wherein the usage pattern is determined based on analyzing a number of past workloads of the CMB and a current workload of the CMB, as claimed. Although the combination of shin teaches utilize the portion of the CMB to store non-host data, nevertheless, the combination of Shin does not explicitly teach the utilization of the portion of CMB is based on the determining step, as claimed.
However, the combination of Shin in view of Holmes teaches determine whether a portion of the CMB can be used by the controller based on a usage pattern of the CMB by the host device (Holmes, col.8, line 60- col.9, line 19, The priority cache 606 may be logically divided into cache regions; col.9, lines 20-39, the unused portion of the reservation of a cache region may be borrowed or reallocated to one or more of the other cache regions.), wherein the usage pattern is determined based on analyzing a number of past workloads of the CMB and a current workload of the CMB (Holmes, col.9, lines 20-39, For example if a cache region has a reservation of ten (10) data entries but its associated LRU linked list contains only seven (7) data entries, then the remaining unused space (for three (3) data entries) may be available for use with the other cache regions);
utilize the portion of the CMB to store non-host data based on the determining (Holmes, col.9, lines 20-39, the unused portion of the reservation of a cache region may be borrowed or reallocated to one or more of the other cache regions. For example if a cache region has a reservation of ten (10) data entries but its associated LRU linked list contains only seven (7) data entries, then the remaining unused space (for three (3) data entries) may be available for use with the other cache regions).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shin to incorporate teachings of Holmes to determining whether the current workload results in unused capacity for a buffer partition and the unused capacity can be leased to another user to utilize. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shin with Holmes because it improves efficiency of the storage system disclosed in the combination of Shin by allowing allocated but unused storage space to be utilized by another user instead of being wasted.
The combination of Shin does not explicitly teach the usage pattern is determined based on analyzing a number of past workloads of CMB, as claimed.
However, the combination of Shin in view of Benisty teaches usage pattern is determined based on analyzing a number of past workloads of CMB (Benisty, [0042], The statistics tracking sub-module tracks or monitors one or more parameters relating to transaction requests of DRAM 111 by virtualized host(s) 16; [0061], Credit allocations and the number of credits required for each CMB/PMR transaction may be based on one or more of the following parameters: size of DRAM 111 allocated for each client, priority of each client, priority of the specific transaction, type of storage (e.g., whether type of storage is CMB or PMR), type of usage of the CMB region 230 (e.g., user data, queues), transfer type (e.g., aligned transfers, aligned transfer), transaction size, and timeout duration).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shin to incorporate teachings of Benisty to track usage/performance statistics for controller memory buffer to determine usage patterns which can be used for memory management. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shin with Benisty because it improves efficiency of the storage system disclosed in the combination of Shin by assigning memory to users based on memory usage and availability.
Regarding claim 14, the combination of Shin teaches all the features with respect to claim 13 as outlined above. The combination of Shin further teaches the data storage device of claim 13, wherein utilizing the portion of the CMB comprises storing cache data in the portion of the CMB, and wherein the cache data was previously stored external to the controller (Bolkhovitin, [0117], the mapping tables are stored/located in the storage devices, with portions stored in CMBs of the main controller subsystem for fast access).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Shin to incorporate teachings of Bolkhovitin to store portions of storage address mapping tables in one or more controller memory buffers. A person of ordinary skill in the art would have been motivated to combine the teachings of Shin with Bolkhovitin because it improves performance of the storage system disclosed in Shin by providing fast access to mapping tables associated with the storage system (Bolkhovitin, [0117]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shin, Bolkhovitin, Holmes, and Benisty as applied to claim 13 above, and further in view of Chaudhari et al. (US2004/0068615), hereinafter Chaudhari.
Regarding claim 15, the combination of Shin teaches all the features with respect to claim 13 as outlined above. The combination of Shin does not explicitly teach the data storage device of claim 13, wherein utilizing the portion of the CMB comprises storing second read look ahead data in the portion of the CMB, and wherein first read look ahead data is stored in the controller external to the CMB, as claimed.
However, the combination of Shin in view of Chaudhari teaches the data storage device of claim 13, wherein utilizing the portion of the CMB comprises storing second read look ahead data in the portion of the CMB, and wherein first read look ahead data is stored in the controller external to the CMB (Chaudhair, [0017]; Fig.1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shin to incorporate teachings of Chaudhair to store a first prefetched data to a first buffer in a storage controller and store a second prefetched data to a second buffer. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shin with Chaudhari because it improves efficiency and performance of the storage system disclosed in the combination of Shin by allowing a second prefetch operation to be processed before the completion of storing the first prefetch data.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shin, Bolkhovitin, Holmes, and Benisty as applied to claim 13 above, and further in view of Yoo et al. (US2023/0153038), hereinafter Yoo.
Regarding claim 16, the combination of Shin teaches all the features with respect to claim 13 as outlined above. The combination of Shin does not explicitly teach the data storage device of claim 13, wherein utilizing the portion of the CMB comprises storing at least a portion of a relink table in the portion of the CMB, and wherein the relink table maps bad blocks of the memory device to good blocks of the memory device, as claimed.
However, the combination of Shin in view of Yoo teaches the data storage device of claim 13, wherein utilizing the portion of the CMB comprises storing at least a portion of a relink table in the portion of the CMB, and wherein the relink table maps bad blocks of the memory device to good blocks of the memory device (Bolkhovitin, [0117]; Yoo, [0072], the data mapping may mean transferring data in the bad memory block to the free memory block and updating the address mapping of the logical address of the bad block to be associated with the physical address of the new (previously free) block (e.g., in FTL 311_4, such as in a physical to logical mapping table of FTL 311_4).).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shin to incorporate teachings of Yoo to include bad block mapping tables and store the bad block mapping tables in controller memory buffer. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shin with Yoo because it improves reliability and performance of the storage system disclosed in the combination of Shin by mapping bad data blocks to free data blocks in order to prevent/reduce data loss in the bad data blocks (Yoo, [0072]).
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shin, Bolkhovitin, Holmes, and Benisty as applied to claim 13 above, and further in view of Kachare et al. (US2019/0317901), hereinafter Kachare.
Regarding claim 17, the combination of Shin teaches all the features with respect to claim 13 as outlined above. The combination of Shin does not explicitly teach the data storage device of claim 13, wherein the controller is configured to identify a usage pattern of host data stored in the portion of the CMB as cold data, wherein cold data is data that is not expected to be read during a subsequent time frame, as claimed.
However, the combination of Shin in view of Kachare teaches the data storage device of claim 13, wherein the controller is configured to identify a usage pattern of host data stored in the portion of the CMB as cold data, wherein cold data is data that is not expected to be read during a subsequent time frame (Kachare [0045]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shin to incorporate teachings of Kachare to identify a cache block with the lowest probability of imminent access and evict the identified cache block from the cache if needed. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shin with Kachare because it improves efficiency and performance of the storage system disclosed in the combination of Shin by reducing the frequency of moving data into and out of a cache.
Regarding claim 19, the combination of Shin teaches all the features with respect to claim 17 as outlined above. The combination of Shin further teach the data storage device of claim 17, wherein the controller is further configured to: determine that the host device is attempting to read the host data identified as cold data from the CMB (Shin, [0064], The host 2000 may input read command to the memory system 1000. The memory controller 1200 of the memory system 1000 may first check whether data corresponding to the read command input from the host 2000 has been stored in the completion queue 7212 of the controller memory buffer 721 in response to the read command.); provide the host data identified as cold data from the memory device to the host device; and return the host data identified as cold data to the CMB (Shin, [0067], the memory controller 1200 may read the data corresponding to the read command, which is stored in the memory device 1100. The memory controller 1200 may control the data corresponding to the read command, which is output from the memory device 1100, to be transferred to the completion queue 7212, and set the completion queue 7212 indicating that the processing of the read command has been completed. Subsequently, the host 2000 may receive the data corresponding to the read command from the completion queue 7212).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shin, Bolkhovitin, Holmes, Benisty, and Kachare as applied to claim 17 above, and further in view of Hepkin (US2009/0307686), hereinafter Hepkin.
Regarding claim 18, the combination of Shin teaches all the features with respect to claim 17 as outlined above. The combination of Shin does not explicitly teach the data storage device of claim 17, wherein the controller is configured to move the host data identified as cold data to the memory device prior to the utilizing, wherein the host data identified as cold data uses less than all of the portion of the CMB, as claimed.
However, the combination of Shin in view of Hepkin teaches the data storage device of claim 17, wherein the controller is configured to move the host data identified as cold data to the memory device prior to the utilizing, wherein the host data identified as cold data uses less than all of the portion of the CMB (Hepkin, [0012], A virtual machine receives a request for memory donation. A component of the virtual machine determines whether a portion of a memory space being used for file caching exceeds a threshold … If the threshold determination is true, a component of the virtual machine releases a part of the file cache that exceeds the threshold … the virtual machine makes the released file cache available to a requester of the request; [0080]; Fig.6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shin to incorporate teachings of Hepkin to flush data from a volatile memory to a persistent storage in response to a memory donation request in order to release a portion or the volatile memory for a requestor. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shin with Hepkin because it improves efficiency of the storage system disclosed in the combination of Shin by sharing memory storage among different requestors.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Shin, Bolkhovitin, Holmes, Benisty, and Kachare as applied to claim 19 above, and further in view of Furuya (US6,628,936), hereinafter Furuya.
Regarding claim 20, the combination of Shin teaches all the features with respect to claim 19 as outlined above. The combination of Shin does not explicitly teach the data storage device of claim 19, wherein the controller is further controller to: check an importance of the non-host data utilizing the portion of the CMB; and determine whether to delete the non-host data based on the importance of the non-host data in response to the returning of the host data identified as cold data to the CMB, as claimed.
However, the combination of Shin in view of Furuya teaches the data storage device of claim 19, wherein the controller is further controller to: check an importance of the non-host data utilizing the portion of the CMB; and determine whether to delete the non-host data based on the importance of the non-host data in response to the returning of the host data identified as cold data to the CMB (Furuya, col.1, lines 29-36, data to be deleted when new data is received is determined according to a predetermined priority order depending on conditions such as data which is not set in data delete prohibition (to be referred to as protect hereinafter) or data; Note – if the non-host data is protected/higher priority, then the non-host data is not to be deleted.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Shin to incorporate teachings of Furuya to check whether a first data currently stored in a buffer is protected or having a higher priority than a second data and if the first data is protected/having high priority, then the second data cannot overwrite the first data. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Shin with Furuya because it improves flexibility of the storage system disclosed in the combination of Shin by allowing the storage system to set priority on stored data in order to determine the retainability of the data.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Malakapalli et al. (US2022/0291861) teaches a controller memory buffer (drive buffer) is accessible to both a host device and a memory controller. The controller memory buffer stores non-host data such as computation result of a compute function.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCI N WONG whose telephone number is (571)272-4117. The examiner can normally be reached Monday-Friday 9am -6pm.
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/NANCI N WONG/Primary Examiner, Art Unit 2137
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