Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6, 9, 15-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. 2024/0029651.
Regarding claim 1, Kim et al. 2024/0029651, figs. 1, 15, discloses a display device, comprising: a display panel on which a plurality of data lines (, a plurality of gate lines, a plurality of power lines, and a plurality of pixels are disposed on a substrate; a data driver configured to output a data voltage of pixel data to one of the plurality of data lines; and a gate driver configured to supply a gate signal to one of the plurality of gate lines sequentially, wherein each of the plurality of pixels (The display panel 10 may include a display area or an active area AA and a non-display area or a non-active area N/A. A plurality of pixels P may be disposed in the display area A/A of the display panel 10. For example, a plurality of gate lines GL and a plurality of data lines DL may be disposed in the display panel 10, and the pixel P may be disposed in an area where the gate line GL and the data line DL intersect each other. Each pixel P may include at least one of sub-pixels SP respectively emitting light beams of red (R), green (G), and blue (B) colors, but the embodiment of present disclosure is not limited thereto. For example, each pixel P may also include at least one of sub-pixels SP respectively emitting light beams of white (W), red (R), green (G), and blue (B) colors) comprises: a light emitting element including a first electrode, a second electrode facing the first electrode, and a light emitting layer disposed between the first electrode and the second electrode (FIG. 15, the light-emitting element 170 including the light-emitting layer 172 may be disposed on the second middle layer 160 and a bank layer 165. The light-emitting element 170 may include the anode electrode 171, at least one light-emitting layer 172 formed on the anode electrode 171, and the cathode electrode 173 formed on the light-emitting layer 172); a driving element configured to control the light emitting element; and a plurality of switching elements configured to control the driving element, and wherein the driving element includes an oxide semiconductor layer (The source electrode 140 may be connected to the exposed source area of the semiconductor layer 115 via the contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may be opposite to the source electrode 140 and may be connected to the drain area of the semiconductor layer 115 via the contact hole extending through the second insulating layer 120 and the third insulating layer 135).
Regarding claim 6, Kim et al. 2024/0029651, figs. 1, 15, discloses display device of claim 1, wherein a driving period of each of the plurality of pixels includes a refresh period, an anode reset period, and a light emission control period, wherein a threshold voltage of the driving element is sensed and compensated during the refresh period, wherein the first electrode of the light emitting element is reset to an anode reset voltage during the anode reset period, and wherein the light emission control period is disposed between the refresh period and the anode reset period (see pars.73, 1125, 135, 165, 315).
Regarding claim 9, Kim et al. 2024/0029651, figs. 1, 2, 15, discloses the display device of claim 1, wherein the plurality of switching elements includes: a first transistor configured to include a poly semiconductor layer; and a second transistor configured to include an oxide semiconductor layer, and wherein the poly semiconductor layer is disposed as a lower layer than the oxide semiconductor layer (see pars. 102, 103, 200, 304).
Regarding claims 15, 16, Kim et al. 2024/0029651, figs. 1, 2, 14, discloses the display device of claim 1, wherein the gate driver includes: a first scan driver, a second scan driver, a third scan driver, a first light emission control driver, and a second light emission control driver; and/or wherein the first and the second light emission control drivers are disposed between the first to the third scan drivers (Referring to FIG. 14, in the gate driver 30 including a light-emission control signal driver, a first scan driver, and a second scan driver, stages ST1 to STn of the shift register may include first scan signal generators SC1(1) to SC1(n), second scan signal generators SC2(1) to SC2(n), and light-emission control signal generators EM(1) to EM(n), respectively. In one example, the first stage ST1 of the shift register may include the first scan signal generator SC1(1) outputting a first scan signal SC1(1), the second scan signal generator SC2(1) outputting a second scan signal SC2(1), and the light-emission control signal generator EM(1) that outputs an emitting control signal EM(1)).
Regarding claims 17, 18, Kim et al. 2024/0029651, figs. 1, 2, 14, discloses the display device of claim 15, wherein the first scan driver is configured with: a (1-1)th scan driver configured to supply a first scan signal to an odd-numbered pixel row, and a (1-2)th scan driver configured to supply the first scan signal to an even-numbered pixel row; and/or the second light emission control driver is disposed at an outermost side of the display panel. (Referring to FIG. 14, in the gate driver 30 including a light-emission control signal driver, a first scan driver, and a second scan driver, stages ST1 to STn of the shift register may include first scan signal generators SC1(1) to SC1(n), second scan signal generators SC2(1) to SC2(n), and light-emission control signal generators EM(1) to EM(n), respectively. In one example, the first stage ST1 of the shift register may include the first scan signal generator SC1(1) outputting a first scan signal SC1(1), the second scan signal generator SC2(1) outputting a second scan signal SC2(1), and the light-emission control signal generator EM(1) that outputs an emitting control signal EM(1)).
Allowable Subject Matter
Claims 2-5, 7, 8, 10-14, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of the references cited in record disclose or suggest that the display device of claim 1, wherein each of the plurality of pixels comprises: a first node connected to a first electrode of the driving element, a second node connected to a gate electrode of the driving element, and a third node connected to a second electrode of the driving element; a first capacitor connected between the second node and a fourth node; a second capacitor connected between the third node and the fourth node; a fifth node connected to the first electrode of the light emitting element; a first switching element configured to transmit a data voltage to the second node in response to a first gate signal; a second switching element configured to apply a reference voltage to the second node in response to a second gate signal; and a third switching element configured to apply the reference voltage to the fourth node in response to a third gate signal; and/or the display device of claim 1, wherein the plurality of switching elements includes: a third transistor connected to a first electrode of the driving element; and a fourth transistor connected to a second electrode of the driving element, and wherein the third transistor and the fourth transistor have different semiconductor layers from each other.
Conclusion
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/VAN N CHOW/Primary Examiner, Art Unit 2627