Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Instant application is a continuation of Application No. 18/510540, now U.S. Patent 12,361,119. In a preliminary amendment, claims 1-20 have been canceled; claims 21-40 have been newly added. Claims 21-40 have been examined.
Information Disclosure Statement
2. The information disclosure statements (IDS) submitted on 10/21/2025 and 04/30/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
3. Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,361,119. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application
12,361,119
Claims 21, 28 and 35 –
A processor, comprising:
an execution circuit configured to:
speculatively execute an instruction stream responsive to an unresolved condition,
wherein to speculatively execute the instruction stream the execution circuit is configured to:
defer reporting of an exception condition occurring during execution of an instruction of the instruction stream to generate an observable state unaffected by the exception condition, wherein to generate the observable state the execution circuit is configured to complete execution of at least one instruction of the instruction stream subsequent to the occurring of the exception condition; and
report the exception condition responsive to resolution of the condition.
Claims 1, 10 and 19 –
A processor, comprising: …
an execution circuit configured to
speculatively execute, responsive to an unresolved condition, an instruction stream comprising a plurality of instructions including an instruction comprising authentication of an instruction operand,
wherein to speculatively execute the instruction stream the execution circuit is configured to:
… defer reporting the generated authentication result until resolution of the condition…
generate an observable state of the processor independent of the generated authentication result
…complete speculative execution of the instruction; and speculatively execute at least one additional instruction of the plurality of instructions subsequent to completing speculative execution of the instruction…
(claim 2)
responsive to resolution of the unresolved condition… suspend processor execution at the instruction; and generate a processor fault
Claims 22, 29 and 36
Claim 2
Claims 23, 30 and 37
Claim 3
Claims 24, 31 and 38
Claim 4
Claims 25, 32 and 39
Claim 7
Claims 26 and 33
Claim 8
Claims 27, 34 and 40
Claim 9
For claims 21-40, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the different embodiments of U.S. Patent No. 12,361,119 to include the elements of claim 2. It would have been obvious because combining prior art elements according to known methods would yield the predictable results of reporting a fault in response to resolution of the unresolved condition.
Allowable Subject Matter
4. Claims 21-40 would be allowable with a timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) to overcome the rejection under nonstatutory double patenting set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
For independent claims 21, 28 and 35, the prior art of record, alone or in combination, fails to teach the following limitations in conjunction with the rest of the claimed limitations:
speculatively execute an instruction stream responsive to an unresolved condition, wherein to speculatively execute the instruction stream the execution circuit is configured to: defer reporting of an exception condition occurring during execution of an instruction of the instruction stream to generate an observable state unaffected by the exception condition, wherein to generate the observable state the execution circuit is configured to complete execution of at least one instruction of the instruction stream subsequent to the occurring of the exception condition
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Iles et al. (U.S. Patent Application Publication 2024/0086526) teaches pointer authentication using a signature (note paragraph [0038]). Wherein if a point is found to be not valid during speculative execution, a mitigation action is taken which includes modifying the signature to indicate the pointer is valid (note paragraph [0034]) to mitigate against side channel attacks (note paragraphs [0006]-[0007]). A microarchitectural exception is raised to trigger a pipeline flush when the pointer authentication instruction is ready for retirement (note paragraph [0044]) and then a subsequent iteration of the pointer authentication instruction is no longer speculative, an invalid address exception is triggered (note paragraph [0046]).
Mendelson (U.S. Patent Application Publication 2022/0300610) teaches protecting a speculative execution processor against side channel attacks by storing speculative instructions in an internal cache inaccessible to read actions of an external processing unit during a first time period and copying only committed portions of executed code segments into an accessible memory during a second time period (note paragraphs [0061]-[0062]).
Favor et al. (U.S. Patent Application Publication 2022/0027467) teaches a system that mitigates side channel attacks against speculative execution including stalling an instruction in response to an exception (note paragraphs [0071]-[0072]).
LeMay (U.S. Patent Application Publication 2021/0096872) teaches eliding safety checks during speculative execution (note paragraphs [0030]-[0034]).
LeMay et al. (U.S. Patent Application Publication 2020/0134234) teaches a system that performs speculative execution (note paragraph [0039]) and uses pointer authentication codes (note paragraph [0068]).
Ghose (U.S. Patent Application Publication 2015/0286821) teaches continuous validation of control flow path using a hash signature during speculative execution (note paragraph [0176]).
Krishnaswamy (U.S. Patent Application Publication 2010/0281465) teaches deferring exception handling until a check instruction validates a speculative advanced load (note paragraph [0030]).
Hornung et al. (U.S. Patent Application Publication 2024/0386094) teaches a pointer signature for determining if a predicted pointer is valid (note Abstract).
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J PEARSON whose telephone number is (571)272-0711. The examiner can normally be reached 8:30 - 6:00 pm; Monday through Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Thiaw can be reached at (571)270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DAVID J. PEARSON
Primary Examiner
Art Unit 2407
/David J Pearson/Primary Examiner, Art Unit 2407
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