DETAILED ACTION
Status of Claims
Claims 1 – 20 are pending.
Claims 1, 10 and 15 are independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
Claims 1, 2, 4, 7, 10-13, and 15-17 of this application is patentably indistinct from claim 1,3 , 5, 8 – 11, 14, 15 and 21 of Application No. 18/478355. Pursuant to 37 CFR 1.78(f), when two or more applications filed by the same applicant or assignee contain patentably indistinct claims, elimination of such claims from all but one application may be required in the absence of good and sufficient reason for their retention during pendency in more than one application. Applicant is required to either cancel the patentably indistinct claims from all but one application or maintain a clear line of demarcation between the applications. See MPEP § 822.
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 2, 4, 7, 10-13, and 15-17 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 3, 5, 8 – 11, 14, 15 and 21 of U.S. Patent No. 12,339,729. Although the claims at issue are not identical, they are not patentably distinct from each other because they are directed to the same invention: systems and methods for supply harvesting operations. Power management circuitry may receive a supply voltage from other power management circuitry. This supply voltage may be a harvested supply from the other power management circuitry. Moreover, some of the power management circuitry may be operated as controller power management circuitry to supply the supply voltage via one or more rails and some of the power management circuitry may be operated as leaf power management circuitry to harvest the supply voltage from the one or more rails. Differences of the instant application is provided in the table below [emphasis added by the Examiner].
Instant Application. No. ‘240
Patent No. ‘729
1. A system, comprising: a processing circuitry; and a first package comprising a first power management unit (PMU) configured to supply the processing circuitry with power, wherein the first PMU comprises a terminal operable in a blocking state while decoupled from a power source.
[processing circuitry powered by the PMU is a generic element]
14. A system comprising: a first power management unit (PMU); and a plurality of power management units (PMUs), wherein the plurality of PMUs are configured to, respectively, harvest a voltage from the first PMU and provide the voltage to one or more terminals, and wherein a respective PMU of the plurality of PMUs comprises a general purpose input/output (GPIO) operable in a blocking state while decoupled from a power source.
21. The system of claim 14, comprising a chip package, wherein the chip package comprises a plurality of distinct die including the first PMU and the plurality of PMUs, and wherein one or more distinct die of the plurality of distinct die are communicatively coupled to each other.
The system of claim 1, wherein the first PMU comprises a first pin configured to supply a first voltage to the terminal to preserve the blocking state of the terminal while decoupled from the power source between a first time and a second time, wherein the first voltage is characterized by a threshold level of voltage.
[Pin is an obvious route to supply power]
1. An electronic device comprising: a leaf power management unit (PMU) comprising a general purpose input/output (GPIO) operable in a blocking state while receiving a threshold level of voltage, wherein the leaf PMU is configured to be decoupled from a power source between a first time and a second time and coupled to the power source at the second time; and a controller PMU configured to couple to the leaf PMU, wherein the leaf PMU is configured to supply the threshold level of voltage to the GPIO between the first time and the second time.
The system of claim 4, wherein the processing circuitry is configured to, before entering the retention mode, configure the first PMU to supply a threshold level of voltage to the terminal during the retention mode to preserve the blocking state of the terminal.
[the configuring step by the processing circuitry]
10. The circuitry of claim 8, wherein the digital logic is configured to be operated as part of a retention mode that enables one or more states associated with the digital logic to be maintained while the PMU is decoupled from the power source.
7. The system of claim 1, wherein the first package comprises a second PMU configured to supply the terminal, and wherein the terminal is configured to operate in a bias state that corresponds to a voltage between a well and a gate of the terminal.
[Same well-to-gate language]
8. Circuitry comprising: a power source; a power management unit (PMU) configured to supply a terminal, wherein the terminal is configured to, at at least some times, operate in a bias state that corresponds to a voltage between a well and a gate of the terminal, wherein the PMU is configured to couple to the power source at a first time; and digital logic configured to couple to the PMU, wherein the digital logic is configured to enable an analog domain in response to the PMU being coupled to the power source at the first time, wherein, before the first time, the PMU is configured to receive a threshold amount of power to maintain the terminal in the bias state while the PMU is decoupled from the power source.
10. A tangible, non-transitory, computer-readable medium, comprising computer-readable instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: generate a reset signal to exit from a retention mode, wherein the retention mode corresponds to a digital domain and an analog domain being disabled; and enable the analog domain, the digital domain, or both in response to receiving an event signal from a first power management unit (PMU) after generating the reset signal, wherein the first PMU comprises a terminal and is configured to supply a threshold level of voltage to the terminal during the retention mode to preserve a blocking state of the terminal.
[Reset; both domains disabled]
1. An electronic device comprising: a leaf power management unit (PMU) comprising a general purpose input/output (GPIO) operable in a blocking state while receiving a threshold level of voltage, wherein the leaf PMU is configured to be decoupled from a power source between a first time and a second time and coupled to the power source at the second time; and a controller PMU configured to couple to the leaf PMU, wherein the leaf PMU is configured to supply the threshold level of voltage to the GPIO between the first time and the second time.
The electronic device of claim 1, comprising: the power source; and digital logic configured to couple to the leaf PMU, wherein the digital logic is configured to enable an analog domain at the second time and in response to an event generated by the controller PMU, the leaf PMU, or both, and wherein before the first time, the controller PMU is configured to receive the threshold level of voltage from the leaf PMU to maintain the GPIO in a bias state corresponding to the blocking state while the controller PMU is decoupled from the power source between the first time and the second time.
8. Circuitry comprising: a power source; a power management unit (PMU) configured to supply a terminal, wherein the terminal is configured to, at at least some times, operate in a bias state that corresponds to a voltage between a well and a gate of the terminal, wherein the PMU is configured to couple to the power source at a first time; and digital logic configured to couple to the PMU, wherein the digital logic is configured to enable an analog domain in response to the PMU being coupled to the power source at the first time, wherein, before the first time, the PMU is configured to receive a threshold amount of power to maintain the terminal in the bias state while the PMU is decoupled from the power source.
10. The circuitry of claim 8, wherein the digital logic is configured to be operated as part of a retention mode that enables one or more states associated with the digital logic to be maintained while the PMU is decoupled from the power source.
11. The tangible, non-transitory, computer-readable medium of claim 10, comprising additional computer-readable instructions that, when executed by the one or more processors, cause the electronic device to, before entering the retention mode, configuring the first PMU to harvest the threshold level of voltage from a second PMU.
[The configuration step]
14. A system comprising: a first power management unit (PMU); and a plurality of power management units (PMUs), wherein the plurality of PMUs are configured to, respectively, harvest a voltage from the first PMU and provide the voltage to one or more terminals, and wherein a respective PMU of the plurality of PMUs comprises a general purpose input/output (GPIO) operable in a blocking state while decoupled from a power source.
15. The system of claim 14, wherein a subset of the plurality of PMUs are configured to, respectively, harvest the voltage from the first PMU via direct coupling to the first PMU.
12. The tangible, non-transitory, computer-readable medium of claim 10, wherein the blocking state corresponds to the terminal having a bias between a well and a gate based on the threshold level of voltage.
3. The electronic device of claim 1, wherein the blocking state corresponds to the GPIO having a bias between a well and a gate based on the threshold level of voltage.
13. The tangible, non-transitory, computer-readable medium of claim 12, comprising additional computer-readable instructions that, when executed by the one or more processors, cause the electronic device to enable the terminal, wherein the terminal comprises a general purpose input/output (GPIO).
[the enabling step]
9. The circuitry of claim 8, wherein the terminal comprises a general purpose input/output (GPIO).
15. A circuit comprising: a terminal operable in a blocking state; and a first pin configured to supply a first voltage to the terminal to preserve the blocking state of the terminal between a first time and a second time, wherein the first voltage is characterized by a threshold level of voltage.
[Pin]
8. Circuitry comprising: a power source; a power management unit (PMU) configured to supply a terminal, wherein the terminal is configured to, at least some times, operate in a bias state that corresponds to a voltage between a well and a gate of the terminal, wherein the PMU is configured to couple to the power source at a first time; and digital logic configured to couple to the PMU, wherein the digital logic is configured to enable an analog domain in response to the PMU being coupled to the power source at the first time, wherein, before the first time, the PMU is configured to receive a threshold amount of power to maintain the terminal in the bias state while the PMU is decoupled from the power source.
16. The circuit of claim 15, comprising a regulator configured to be powered down between the first time and the second time.
[The regulator is powered down]
10. The circuitry of claim 8, wherein the digital logic is configured to be operated as part of a retention mode that enables one or more states associated with the digital logic to be maintained while the PMU is decoupled from the power source.
11. The circuitry of claim 10, wherein the PMU comprises a linear or low-dropout (LDO) regulator.
17. The circuit of claim 15, wherein the terminal comprises a general purpose input/output (GPIO).
9. The circuitry of claim 8, wherein the terminal comprises a general purpose input/output (GPIO).
Appropriate action is required.
Allowable Subject Matter
Claims 3, 5,6 8, 9, 14, and 18 -20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kowkutla; Venkateswar et al. (US Patent Application Publication No. 2023/0238872) “Integrated Circuit With Low Power Mode Management” is cited to teach, an integrated circuit (IC) that includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.
Garg; Vivek et al. (US Patent Application Publication No. 2022/0100247) “Hierarchical Power Management Apparatus And Method” is cited to teach Hierarchical Power Management (HPM) architecture that considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F.
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/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
