Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements have been received on 07/18/2025 and 01/12/2026 have been accepted and the references cited within are carefully considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 112(b) as the limitations are not very clear.
Specifically, the limitation “… obtaining, by the authentication control circuit, permission information of a sub-region in which the target address is located from the memory…” is not very clear. Applicant should clarify/amend the limitation with the appropriate support in the specification.
For the purpose of the initial prosecution, the limitation is treated as indicating that the target address is located in the sub-region of the memory.
Appropriate correction/clarification is required.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C 103 as being unpatentable over Zhang (CN101620652B) in view of Grocutt (US20210311884A1).
Regarding claim 1, Zhang discloses a storage controller configured to authenticate an
operation instruction sent by a primary device, wherein the storage controller is coupled to a memory (“control chip units used for transmitting an access instruction when accessing the memory data,” abstract), and the storage controller comprising: a bus parser configured to obtain a to-be performed operation and a target address of the operation by parsing the operation instruction sent by the primary device; an authentication control circuit, (“second control chip unit 102 sends out an access instruction, the access instruction reaches the bus arbitration control unit 103, the bus arbitration control unit 103 judges that the access instruction is from the second control chip unit 102, then reads the corresponding access right in the corresponding register unit 107, the access right indicates that the stored common data is allowed to be written, the bus arbitration control unit 103 sends out a driving signal, the driving signal reaches the write protection pin WP #, and the write operation of the flash memory 104 is allowed by changing the level. The second control chip unit 102 now finds the normal data of the corresponding partition located in the flash memory 104 through the address bus and reads these normal data through the data bus,” Page 6) and, whether permission of the operation satisfies a requirement; and an interface adapter configured to send the operation instruction to the memory when the permission of the operation satisfies the requirement (“The bus arbitration control unit 103 is configured to determine, after receiving the access instruction, which specific control chip unit the flag bit or other identifier in the access instruction comes from, read the access right of the control chip unit in the register unit 105 after the determination, and send out a driving signal according to the access right, where the driving signal reaches the flash memory 104 through the bus.,” Page 6). However, Zhang does not teach the following limitations that Grocutt teaches such as the memory comprises a first region configured to store data of the primary device, the first region comprises a plurality of sub-regions and the authentication control circuit configured to obtain permission information of a sub-region in which the target address is located from the memory, and determine, based on the permission information (“hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 49). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s in order to store permission information in a memory versus completely putting the permission information in register which leads to excessive area for the register.
Regarding claim 2, Zhang in view of Grocutt teach the storage controller of claim 1 as cited earlier. Zhang further teaches the authentication control circuit comprises an authentication circuit and a missing controller, the missing controller and the authentication circuit is configured to determine, based on the permission information, whether the permission of the operation satisfies the requirement (“if a plurality of control chip units exist, different control chip units all need to perform read/write operations on the shared flash memory 104…if the command is from the second control chip unit 102, and the second control chip unit 102 has no authority to write, the bus arbitration control unit 103 sends a signal to the write protect pin WP #, and does not allow the write operation to the flash memory 104,” Page 5-6). Zhang does not teach, but Grocutt teaches the missing controller is configured to obtain the permission information of the sub-region in which the target address is located from the memory (“a hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 49). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s as a way to better deal with memory in a computer and make said system potentially more flexible and secure.
Regarding claim 3, Zhang in view of Grocutt teach the storage controller according to claim 2 as cited earlier. Grocutt further teaches wherein the authentication control circuit further comprises a cache, configured to store permission information of a part of the plurality of sub-regions, and the authentication circuit is further configured to, when the cache stores the permission information of the sub-region in which the target address is located, determine, based on the permission information stored in the cache, whether the permission of the operation satisfies the requirement (“the static MPU register storage…access to a specific sub-region… the MPU may cache a memory protection entry from the memory protection table in a portion of the static MPU register storage corresponding to said given static memory protection entry,” Paragraph 49-50). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s in order to store permission information in a memory in order to make sure that it a system runs more efficiently and make sure that data security stored in memory is guaranteed.
Regarding claim 4, Zhang in view of Grocutt teach the storage controller according to claim 3 as cited earlier. Grocutt further teaches wherein the missing controller is further configured to, when the cache does not store the permission information of the sub-region in which the target address is located, obtain the permission information of the sub-region in which the target address is located from the memory (“in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 50), and store the permission information into the cache (“static memory protection entry is indicated as unused then it may be used as a cache in which case there may be a change in the particular entry provided in the static MPU register storage,” Paragraph 51). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s mostly to better bolster security of the data in transfer and in the event that there is cache loss.
Regarding claim 5, Zhang in view of Grocutt teach the storage controller according to claim 1 as cited earlier. Grocutt further teaches wherein the interface adapter is further configured to send exception information to the primary device when the permission of the operation does not satisfy the requirement (“the target address hits against the static MPU entry but that static MPU entry specifies access permissions which are not satisfied by the memory access request, then at step 128 the memory access request could be rejected. In this case the MPU may trigger signaling of a fault condition or exception,” Paragraph 125). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s mostly to better bolster security of the data that is in transfer.
Regarding claim 6, Zhang discloses a control method, of a storage controller, used to authenticate an operation instruction sent by a primary device, wherein the storage controller is connected to a memory (“control chip units used for transmitting an access instruction when accessing the memory data,” abstract), and the storage controller comprises a bus parser, an authentication control circuit, and an interface adapter, the method comprising: obtaining a to-be-performed operation and a target address of the operation by parsing, by the bus parser, the operation instruction sent by the primary device (“second control chip unit 102 sends out an access instruction, the access instruction reaches the bus arbitration control unit 103, the bus arbitration control unit 103 judges that the access instruction is from the second control chip unit 102, then reads the corresponding access right in the corresponding register unit 107, the access right indicates that the stored common data is allowed to be written, the bus arbitration control unit 103 sends out a driving signal, the driving signal reaches the write protection pin WP #, and the write operation of the flash memory 104 is allowed by changing the level. The second control chip unit 102 now finds the normal data of the corresponding partition located in the flash memory 104 through the address bus and reads these normal data through the data bus,” Page 6) and, whether permission of the operation satisfies a requirement; and sending, by the interface adapter, the operation instruction to the memory in association with the permission of the operation satisfying the requirement (“The bus arbitration control unit 103 is configured to determine, after receiving the access instruction, which specific control chip unit the flag bit or other identifier in the access instruction comes from, read the access right of the control chip unit in the register unit 105 after the determination, and send out a driving signal according to the access right, where the driving signal reaches the flash memory 104 through the bus.,” Page 6). However, Zhang does not teach the following limitations that Grocutt teaches such as the memory having a first region configured to store data of the primary device, the first region comprises a plurality of sub-regions and the authentication control circuit to obtain permission information of a sub-region in which the target address is located from the memory, and determining, based on the permission information (“hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 49). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s as it can potentially reduce overhead versus putting information like the permission information in the register.
Regarding claim 7, Zhang in view of Grocutt teach the method according to claim 6. Zhang further teaches wherein the authentication control circuit comprises a missing controller and an authentication circuit, and determining, by the authentication circuit and based on the permission information, whether the permission of the operation satisfies the requirement (“if a plurality of control chip units exist, different control chip units all need to perform read/write operations on the shared flash memory 104…if the command is from the second control chip unit 102, and the second control chip unit 102 has no authority to write, the bus arbitration control unit 103 sends a signal to the write protect pin WP #, and does not allow the write operation to the flash memory 104,” Page 5-6). Zhang does not teach, but Grocutt teaches the missing controller obtaining the permission information of the sub-region in which the target address is located from the memory (“a hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 49). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s as a way to better deal with large register area and make said system potentially more efficient and secure.
Regarding claim 8, Zhang in view of Grocutt teach the method according to claim 7 as cited earlier. Grocutt further teaches wherein the authentication control circuit further comprises a cache, and determining whether the permission of the operation satisfies the requirement comprises: in association with the cache storing the permission information of the sub-region in which the target address is located, determining, by the authentication circuit and based on the permission information stored in the cache, whether the permission of the operation satisfies the requirement (“the static MPU register storage…access to a specific sub-region… the MPU may cache a memory protection entry from the memory protection table in a portion of the static MPU register storage corresponding to said given static memory protection entry,” Paragraph 49-50). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s in order to make sure that there is a way to better store permission information for efficiency reasons which influences how well a system runs and influences aspects such as decreased power consumption while in operation.
Regarding claim 9, Zhang in view of Grocutt teach the method according to claim 8 as cited earlier. Grocutt further teaches wherein before determining whether the permission of the operation satisfies the requirement, the method further comprises: in association with the cache not storing permission information of the sub-region in which the target address is located, obtaining, by the missing controller circuit, the permission information of the sub-region in which the target address is located from the memory(“in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 50), and storing the permission information into the cache (“static memory protection entry is indicated as unused then it may be used as a cache in which case there may be a change in the particular entry provided in the static MPU register storage,” Paragraph 51). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s mostly to better bolster security of the data in transfer and in the event that there is cache loss.
Regarding claim 10, Zhang in view of Grocutt teach the method according to claim 6 as cited earlier. Grocutt further teaches sending, by the interface adapter, exception information to the primary device in association with the permission of the operation not satisfying the requirement (“the target address hits against the static MPU entry but that static MPU entry specifies access permissions which are not satisfied by the memory access request, then at step 128 the memory access request could be rejected. In this case the MPU may trigger signaling of a fault condition or exception,” Paragraph 125). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s in order to bolster security of data that is going through said process.
Regarding claim 11, Zhang in view of Grocutt teach a storage system comprising a memory and the storage controller according to claim 1 as cited earlier. Grocutt teaches wherein the storage controller is connected to the memory and the memory comprises a first region and a second region, the first region is configured to store data of a primary device, the first region comprises a plurality of sub-regions, and the second region is configured to store permission information of the plurality of sub-regions (“in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 49). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s mostly to better protection of data on top of more efficient performance.
Regarding claim 12, Zhang and Grocutt teach the storage system according to claim 11. Zhang further teaches a micro controller unit (MCU) and at least one processor, wherein the at least one processor is connected to the storage system. (“in today's computer system or embedded system designs…chip units are respectively a CPU and a management engine; at least one register unit for storing the corresponding relationship between each control chip unit and the access authority; the bus arbitration control unit is used for receiving the access instruction,” Background + Disclosure). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s as a way to increase efficiency of the process performed and the system that it runs under to better bolster security of the data handled.
Regarding claim 13, Zhang further teaches in view of Grocutt an electronic device comprising the micro controller unit according to claim 12 (“in today's computer system or embedded system designs…chip units are respectively a CPU and a management engine; at least one register unit for storing the corresponding relationship between each control chip unit and the access authority; the bus arbitration control unit is used for receiving the access instruction,” Background + Disclosure). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s as a way to increase efficiency of said system in order to run operations and instructions more efficiently.
Regarding claim 14, Zhang teaches a non-transitory computer readable storage medium configured to store computer readable instructions that, when executed by a processor, cause the processor to provide execution comprising: (“FLASH memory (FLASH) is a common memory in today's computer system or embedded system designs,” Background) obtaining a to-be-performed operation and a target address of the operation by parsing an operation instruction sent by a primary device; (“second control chip unit 102 sends out an access instruction, the access instruction reaches the bus arbitration control unit 103, the bus arbitration control unit 103 judges that the access instruction is from the second control chip unit 102, then reads the corresponding access right in the corresponding register unit,” Page 6) and determining, based on the permission information, whether permission of the operation satisfies a requirement; and sending the operation instruction to the memory in association with the permission of the operation satisfying the requirement (“The bus arbitration control unit 103 is configured to determine, after receiving the access instruction, which specific control chip unit the flag bit or other identifier in the access instruction comes from, read the access right of the control chip unit in the register unit 105 after the determination, and send out a driving signal according to the access right, where the driving signal reaches the flash memory 104 through the bus.,” Page 6). However, Zhang does not teach obtaining permission information of a sub-region in which the target address is located from a memory. But, Grocutt teaches obtaining permission information of a sub-region in which the target address is located from a memory (“hit in the static MPU register storage when the request is allowed overrides any permissions set in the memory-based memory protection entries, but a hit in the static MPU register storage when the request is not allowed by the static entry can be overridden by other access permissions specified in a matching memory protection entry of the memory protection table. This approach can be useful to reduce the total number of regions which need to be defined to allow a first software process access to a specific sub-region of an address region accessed by a second software process,” Paragraph 49). It would have been obvious to one of ordinary skill in the art at the time the application was filed to include Grocutt’s teachings into Zhang’s as storing permission information in a non-transitory computer readable memory like flash memory is better to reduce overhead and ideally increase security of information sent along with permission information.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HENRY W CHEUNG whose telephone number is (571)270-0502. The examiner can normally be reached Monday - Friday 8:30 a.m -5:30 p.m ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Pwu can be reached at 571-272-6798. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
HENRY W. CHEUNG
Examiner
Art Unit 2433
/PIOTR POLTORAK/Primary Examiner, Art Unit 2433
Prosecution Insights