Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Claim(s) 1-20 is/are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 22, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al, Korean Patent Publication No. KR20040090128 (English translation listed on IDS dated October 22, 2025) in view of Tsuchi et al, U.S. Patent No. 5818406.
Consider claim 1, Jang teaches a system (see Jang figure 2, and paragraph 0075 where figure 2 illustrates liquid crystal display) comprising:
a plurality of addressable display elements comprising a plurality of subsets (see Jang figure 2, element TFT, GL1-GLn and paragraphs 0029-0030 where pixels connected to TFTs correspond to addressable display elements and a row of pixel connected to a scan signal line GL1-Gln corresponds to a subset of addressable display elements);
a shift register comprising a first plurality of flip flops each coupled to a first clock input (see Jang figure 3, element 132 and paragraph 0033 where shift register array 132 composed of n shift registers SR1-SRn to which clocks Clk1 to Clk4 are supplied. where SR1-SRn correspond to flip flops and paragraph 0036 where shift registers SR1 to SRn receive three clock signals among the first to fourth clock signals Clk1 to Clk4 which are sequentially delayed in phase. Examiner takes Official notice that it is well known that a shift register element may be formed by having a plurality of flip-flops as evidenced by Kubota et al, U.S. Patent Publication No. 20010011987 paragraph 0011 and figure 12; Washio et al, U.S. Patent Publication No. 20010033261 figure 13 and paragraph 0178; and Kwan et al, U.S. Patent Publication No. 20100006783 figure 5 and paragraph 0056. One of ordinary skill would have been motivated to have a plurality of flip-flops so form a shift register using known techniques with predictable results);
a second plurality of flip flops each configured to receive an output from a respective one of the first plurality of flip flops, each of the second plurality of flip flops being coupled to a second clock input (see Jang figure 3, element 132, LS1-LSn and paragraph 0033 where level shifter array 134 composed of then level shifters LS1 to LSn connected to the output terminals of the shift registers SR1 to SRn and paragraph 0036 where the remaining one of the first to fourth clock signals Clk1 to Clk4 is supplied to the level shifters LS1 to LSn), and
each of the second plurality of flip flops configured to output a gate signal to a respective subset of the plurality of subsets of the plurality of addressable display elements (see Jang figure 3, element GL1-GLn and paragraph 0041, 0048 where signals are output to GL1-GLn); and
a controller (see Jang figure 2, element 108) configured to control, by controlling a frequency of the first clock input, which one or more subsets of the plurality of addressable display elements simultaneously receive the gate signal from flip flops of the second plurality of flip flops (see Jang paragraph 0031 where timing controller 108 is configured to change the scan pulse output from the gate driver 106 according to the resolution of the video data or the resolution of the video data displayed on the liquid crystal panel and paragraphs 0044-0054 and figures 4-5 where in high resolution mode, the gate driver is controlled to sequentially output scan pulses to gate lines GL1-GLn as in figure 4 and in low resolution mode, the gate driver is controlled to sequentially output scan pulse to gate lines GL1-GLn in units of two scan lines at a time as in figure 5).
Jang does not specifically indicate that level shift elements correspond to flip flops. In a related field of endeavor, Tsuchi teaches a flip-flop type level shifter (see Tsuchi column 8, lines 44-53 and figure 14 where the shown level shifter is a flip-flop type). One of ordinary skill would have been motivated to have modified Jang to have a flip-flop type level shifter as disclosed by Tsuchi so as to facilitate level shifting a signal using known techniques with predictable results.
Consider claim 2, Jang as modified by Tsuchi teaches all the limitations of claim 1 and further teaches wherein the plurality of addressable display elements are arranged in a grid (see Jang figure 2 where pixels are arranged in a plurality of rows and columns), and
wherein the plurality of subsets of the plurality of addressable display elements are rows of addressable display elements in the grid (see Jang figure 2, elements GL1-GLn rows of pixel are connected to each scan line).
Consider claim 3, Jang as modified by Tsuchi teaches all the limitations of claim 1 and further teaches wherein the plurality of subsets of the plurality of addressable display elements is a plurality of first subsets of the plurality of addressable display elements (see Jang figure 2, elements GL1-GLn rows of pixel are connected to each scan line), wherein the controller is further configured to send a display signal to selected ones of a plurality of second subsets of the plurality of addressable display elements (see Jang figure 2, element GL1-GLn, DL1-DLn paragraphs 0029, 0032 where data driver 104 outputs one pixel signal for one line per horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 108. Where second subset corresponds to columns of pixels), and
wherein each of the plurality of second subsets intersects each of the plurality of first subsets (see Jang figure 2 where data lines are connected to pixels in a column and the columns intersect the rows).
Consider claim 4, Jang as modified by Tsuchi teaches all the limitations of claim 3 and further teaches wherein the plurality of addressable display elements are arranged in a grid (see Jang figure 2 where pixels are arranged in a plurality of rows and columns), and
wherein the plurality of first subsets are a plurality of rows of addressable display elements in the grid (see Jang figure 2 where rows of pixels are connected to each of GL1-GLn) and
wherein the plurality of second subsets are a plurality of columns of the addressable display elements in the grid (see Jang figure 2 where columns of pixels are connected to each of DL1-DLn).
Consider claim 5, Jang as modified by Tsuchi teaches all the limitations of claim 3 and further teaches wherein the display signal controls a brightness and/or color of light to be emitted by display elements in the plurality of second subsets of the plurality of addressable display elements that also receive the gate signal from one or more flip flops of the second plurality of flip flops (see Jang paragraphs 0030-0032 where video data R, G, B corresponds to color and the liquid crystal cell realizes gray (brightness) by adjusting light transmittance by varying an arrangement state of liquid crystals).
Consider claim 6, Jang as modified by Tsuchi teaches all the limitations of claim 1 and further teaches wherein the frequency of the first clock input is an integer multiple of a frequency of the second clock input (see Jang paragraph 0041 where each of the level shifters LS1 to LSn level-shifts signals output from the
shift registers SR1 to SRn in response to the remaining one of the four
clock signals Clk1 to Clk4. And paragraphs 0049-0053 specifically for example paragraph 0052-0053 where two scan pulses having a width twice
the first width are simultaneously output and two scan pulses are
sequentially output. Therefore in the low resolution mode, the output frequency is at least half of the input frequency ).
Consider claim 7, Jang as modified by Tsuchi teaches all the limitations of claim 1 and further teaches wherein at least some of the first plurality of flip flops in the shift register are configured to receive an input from the output of another of the first plurality of flip flops (see Jang figure 3 where SR2 receives an output from SR1 through QC1 and SR3 receives and output from SR1 through Qo1).
Consider claim 8, Jang as modified by Tsuchi teaches all the limitations of claim 1 and further teaches wherein a first flip flop (see Jang figure 3, element SR1) in the first plurality of flip flops (see Jang figure 3, element SR1-SRn) in the shift register is configured to receive an input pattern signal (see Jang figure 3, Vst and paragraph 0033 where start pulse Vst is supplied as shown in figure 3), and wherein each of the first plurality of flip flops other than the first flip flop is configured to receive an input from the output of another of the first plurality of flip flops (see Jang figure 3, each flip flop SR2-SRn receives an input form the output of another of the first plurality of flip flops).
Consider claim 20, Jang teaches a system (see Jang figure 2, and paragraph 0075 where figure 2 illustrates liquid crystal display) comprising:
a plurality of addressable display elements arranged in a plurality of rows and a plurality of columns (see Jang figure 2 where pixels are arranged in a plurality of rows and columns);
a shift register comprising a first plurality of flip flops each coupled to a first clock input (see Jang figure 3, element 132 and paragraph 0033 where shift register array 132 composed of n shift registers SR1-SRn to which clocks Clk1 to Clk4 are supplied. where SR1-SRn correspond to flip flops and paragraph 0036 where shift registers SR1 to SRn receive three clock signals among the first to fourth clock signals Clk1 to Clk4 which are sequentially delayed in phase. Examiner takes Official notice that it is well known that a shift register element may be formed by having a plurality of flip-flops as evidenced by Kubota et al, U.S. Patent Publication No. 20010011987 paragraph 0011 and figure 12; Washio et al, U.S. Patent Publication No. 20010033261 figure 13 and paragraph 0178; and Kwan et al, U.S. Patent Publication No. 20100006783 figure 5 and paragraph 0056. One of ordinary skill would have been motivated to have a plurality of flip-flops so form a shift register using known techniques with predictable results);
a second plurality of flip flops each configured to receive an output from a respective one of the first plurality of flip flops, each of the second plurality of flip flops being coupled to a second clock input (see Jang figure 3, element 132, LS1-LSn and paragraph 0033 where level shifter array 134 composed of then level shifters LS1 to LSn connected to the output terminals of the shift registers SR1 to SRn and paragraph 0036 where the remaining one of the first to fourth clock signals Clk1 to Clk4 is supplied to the level shifters LS1 to LSn), and
each of the second plurality of flip flops configured to output a gate signal to a respective row of the plurality of rows of the plurality of addressable display elements (see Jang figure 3, element GL1-GLn and paragraph 0041, 0048 where signals are output to GL1-GLn); and
a controller (see Jang figure 2, element 108) configured to control, by controlling a frequency of the first clock input, which one or more rows of the plurality of addressable display elements simultaneously receive the gate signal from flip flops of the second plurality of flip flops (see Jang paragraph 0031 where timing controller 108 is configured to change the scan pulse output from the gate driver 106 according to the resolution of the video data or the resolution of the video data displayed on the liquid crystal panel and paragraphs 0044-0054 and figures 4-5 where in high resolution mode, the gate driver is controlled to sequentially output scan pulses to gate lines GL1-GLn as in figure 4 and in low resolution mode, the gate driver is controlled to sequentially output scan pulse to gate lines GL1-GLn in units of two scan lines at a time as in figure 5).
Jang does not specifically indicate that level shift elements correspond to flip flops. In a related field of endeavor, Tsuchi teaches a flip-flop type level shifter (see Tsuchi column 8, lines 44-53 and figure 14 where the shown level shifter is a flip-flop type). One of ordinary skill would have been motivated to have modified Jang to have a flip-flop type level shifter as disclosed by Tsuchi so as to facilitate level shifting a signal using known techniques with predictable results.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al, Korean Patent Publication No. KR20040090128 (English translation) and Tsuchi et al, U.S. Patent No. 5818406 in view of Tseng et al, U.S. Patent Publication No. 20160148556 and Zheng et al, U.S. Patent Publication No. 20160300546.
Consider claim 10, Jang as modified by Tsuchi teaches all the limitations of claim 1. Jang is silent regarding wherein the controller, the shift register and the second plurality of flip flops are implemented as an integrated circuit. In a related field of endeavor, Tseng teaches shift registers may be inside a gate driver integrated circuit (IC) or be formed on the TFT array substrate (see Tseng paragraph 0027) so as to facilitate providing gate signals to a display. Further in a related field of endeavor, Zheng teaches a gate driver integrated circuit containing a controller (see Zheng paragraph 0037) so as to provide control signals.
One of ordinary skill would have been motivated to have provided an integrated circuit including shift registers and controller so as to provide desired controls signals and gate signals to a display using known techniques with predictable results.
Allowable Subject Matter
Claims 11-19 are allowed.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The claimed invention recites
Claim 9 “ wherein the controller is configured to adjust the frequency of the first clock input while the plurality of addressable display elements are operated to produce an image frame by successively providing the gate signal to each of the plurality of subsets of the plurality of addressable display elements ”
Claim 11 “ A method comprising: providing an input pattern to a shift register comprising a first plurality of flip flops each operating according to a first clock frequency; producing first gate signals from a first subset of a second plurality of flip flops each configured to receive an output from a respective one of the first plurality of flip flops; directing each of the first gate signals to respective rows of display elements in a grid of display elements; increasing or decreasing the first clock frequency; and producing second gate signals from a second subset of the second plurality of flip flops, wherein a number of the second plurality of flip flops in the first subset is different from a number of the second plurality of flip flops in the second subset.”
The following prior arts are representative of the state of the prior art:
Jang et al, Korean Patent Publication No. KR20040090128 (English translation) (figures 2-5)
Eom, U.S. Patent Publication No. 20050285827 (figure 8, 12, 14
Kwon et al, U.S. Patent Publication No. 20100006783 (figure 4)
The prior arts cited fails to fairly teach or suggest the combined features of the invention including the recited features of dependent claim 9 and “increasing or decreasing the first clock frequency; and producing second gate signals from a second subset of the second plurality of flip flops, wherein a number of the second plurality of flip flops in the first subset is different from a number of the second plurality of flip flops in the second subset” of independent claim 11. Dependent claims 12-19 are allowable by virtue of being dependent upon a claim reciting allowable subject matter.
These features find support at least at figures 4-5 of Applicant’s original specification.
As such, modification of the prior art of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art would have made the necessary modifications to the prior art of record to encompass the limitations set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 11-19 are allowed and claim 9 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Horibata, U.S. Patent Publication No. 20080204436 (display device), Watanabe, U.S. Patent Publication No. 20100220094 (scan signal line driver), Park et al, U.S. Patent Publication No. 20130050161 (scan driver), Qing et al, U.S. Patent Publication No. 20160365050 (shift register unit).
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/Dorothy Harris/Primary Examiner, Art Unit 2625
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