Prosecution Insights
Last updated: October 02, 2026
Application No. 19/242,196

SINGLE-LEVEL CELL CACHING NOTIFICATION

Non-Final OA §102§103
Filed
Jun 18, 2025
Priority
Jun 19, 2024 — provisional 63/661,673
Examiner
YU, JAE UN
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
671 granted / 747 resolved
+34.8% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
18 currently pending
Career history
767
Total Applications
across all art units

Statute-Specific Performance

§101
5.2%
-34.8% vs TC avg
§103
51.3%
+11.3% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 747 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1, 6-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 2016/0321174), “Li”. 2. As per claim 1, Li discloses a set of memory components of a memory sub-system [Drive Controller 300 including memory components 302 & 304, figure 3]; and a processing device [Host 320, figure 3] operatively coupled to the set of memory components [Drive Controller 300 including memory components 302 & 304, figure 3], the processing device being configured to perform operations comprising: storing data in a storage tier associated with a first type of storage [storing data in a cache tier, figure 3]; determining an amount of space remaining in the storage tier for storing additional data [determining available cache space for data write, step 615, figure 6]; and transmitting a message to a host system representing the amount of space remaining in the storage tier for storing the additional data [a host aware of the available cache space for data write, abstract]. 3. As per claim 6, Li discloses receiving a request from the host system for health status of the memory sub-system [step 625, figure 6]; and in response to receiving the request, transmitting the message to the host system representing the amount of space remaining in the storage tier for storing the additional data [a host aware of the available cache space for data write, abstract]. 4. As per claim 7, Li discloses wherein the message is transmitted as part of a Self-Monitoring, Analysis, and Reporting Technology (SMART) log [a host aware of the available cache space for data write, abstract] [The term “SMART log” needs to be further defined in the claim language]. 5. As per claim 8, Li discloses selectively adding information to the SMART log representing the amount of space remaining in the storage tier [determining available cache space for data write, step 615, figure 6]. 6. As per claim 9, Li discloses comparing the amount of space remaining in the storage tier to a threshold amount [determining available cache space for data write, step 615, figure 6]; and in response to determining that the amount of space remaining in the storage tier fails to transgress the threshold amount, adding the information to the SMART log indicating that the amount of space remaining in the storage tier fails to transgress the threshold amount [a host aware of the available cache space for data write, abstract]. 7. As per claim 10, Li discloses comparing the amount of space remaining in the storage tier to a threshold amount [determining available cache space for data write, step 615, figure 6]; and in response to determining that the amount of space remaining in the storage tier transgresses the threshold amount, excluding the information from the SMART log to indicate to the host system that the amount of space remaining in the storage tier transgresses the threshold amount [a host aware of the available cache space for data write, abstract]. 8. As per claim 11, Li discloses generating a Self-Monitoring, Analysis, and Reporting Technology (SMART) log [a host aware of the available cache space for data write, abstract] [The term “SMART log” needs to be further defined in the claim language]; and periodically sending the SMART log to the host system, the SMART log selectively comprising the message representing the amount of space remaining in the storage tier for storing the additional data [a host aware of the available cache space for data write, abstract]. 9. As per claim 12, Li discloses selectively adding information to the SMART log representing the amount of space remaining in the storage tier [determining available cache space for data write, step 615, figure 6]. 10. As per claim 13, Li discloses causing the host system to delay sending one or more write requests to the memory sub-system based on the message representing the amount of space remaining in the storage tier for storing the additional data [delaying write operation until sufficient space is available, figure 6]. 11. As per claim 14, Li discloses wherein the host system resumes sending the one or more write requests in response to determining that the amount of space remaining in the storage tier transgresses a threshold amount [resuming write operation when sufficient space is available, figure 6]. 12. As per claim 15, Li discloses wherein the threshold amount comprises a five percent of an entire size of the storage tier [Such amount is merely a design choice]. 13. As per claims 16 and 20, the examiner directs the applicant’s attention to claim rejection above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 1. Claims 2-5 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2016/0321174), “Li”, in view of Tanpairoj et al. (US 2019/0369899), “Tanpairoj”. 2. As per claim 2, Li discloses the operations comprising: transmitting the message to the host system [a host aware of the available cache space for data write, abstract]. Li does not disclose expressly transferring the data stored in the storage tier to (the set of memory components associated with) a second type of storage. Tanpairoj discloses transferring data from an SLC to an MLC in the abstract. Li and Tanpairoj are analogous art because they are from the same field of endeavor of caching. Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Li by including the data transfer including the SLC and the MLC as taught by Tanpairoj in the abstract. The motivation for doing so would have been higher storage density as expressly taught by Tanpairoj in paragraph 9. 3. As per claim 3, the cited prior arts disclose wherein the first type of storage comprises single-level cell (SLC) storage [SLC, abstract, Tanpairoj]. 4. As per claim 4, the cited prior arts disclose wherein the second type of storage comprises tri-level cell (TLC) storage or quad-level cell (QLC) storage [paragraph 9, Tanpairoj]. 5. As per claim 5, the cited prior arts disclose the operations comprising: transferring the data stored in the storage tier to the set of memory components associated with the second type of storage [transferring data from a SLC to a MLC, abstract, Tanpairoj]; and preventing processing write requests while transferring the data stored in the storage tier to the set of memory components associated with the second type of storage [delaying write operation until sufficient space is available, figure 6, Li]. 6. As per claims 17-19, the examiner directs the applicant’s attention to claim rejection above. Conclusion A. Claims Rejected Claims 1-20 are rejected. B. Direction for Future Remarks Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAE U YU/Primary Examiner, Art Unit 2138
Read full office action

Prosecution Timeline

Jun 18, 2025
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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4y 1m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.8%)
2y 6m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 747 resolved cases by this examiner. Grant probability derived from career allowance rate.

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