CTNF 19/242,262 CTNF 90250 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are pending in the instant application. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 06/18/2025 is being considered by the examiner. Claim Objections 07-29-01 AIA Claim 19 is objected to because of the following informalities: Claim 19, line 4, recites “ a first data signal”. Examiner suggest “ the first data signal”, since the phrase previously appears in claim 15 . Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2 and 9 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Park et al. (US 20230066738 A1 , hereinafter referenced as Park) . Regarding Claim 1 , Park teaches a display device ( see Fig. 1, Fig. 8, display device 100, para. [0286] ) comprising: a display panel ( see Fig. 1, Fig. 8, display panel 110 ) including a plurality of pixels ( see Figs. 1-2, subpixels SP, Fig. 8, edge subpixels ESP, para. [0286]. Each of the plurality of subpixels SP can include a driving transistor DRT and an emitting element ED ) connected to a plurality of data lines ( see Figs. 1-2, Fig. 8, a plurality of data lines DL, para. [0035] ) and a plurality of return lines ( see Fig. 2, para. [0072], para. [0110], para. [0286]. The reference voltage line RVL will also be referred to as a sensing line. The display panel 110 can further include a plurality of reference voltage lines RVL each electrically connected to a sensing node at which the driving transistor DRT is electrically connected to the emitting element ED ); a timing controller ( see Fig. 1, Figs. 8-9, timing controller140, para. [0052] ) configured to generate first image data corresponding to a first selection pixel connected to a first data line among the plurality of data lines and a first return line among the plurality of return lines ( see Fig. 2, Fig. 9, para. [0190]-[0196]. Referring to FIG. 9, while the display panel 110 is displaying an image of the Nth frame (where N is a positive integer greater than or equal to 1), image data of the (N+1)th frame is input to the timing controller 140. The timing controller 140 can perform a “real-time sensing subpixel selecting process” by receiving the image data of the (N+1)th frame, in order to device which subpixels to sense or not to sense (e.g., subpixels not selected for sensing can be sensed at a later time when gray values of a subsequent frame are more favorable, in which sensing during or immediately before dark periods or dark portions can be avoided, and rescheduled for a later time) ); and a data driver ( see Fig. 1, Figs. 8-9, data driver 120, para. [0037]-[0038] ) configured to apply a first data signal corresponding to a measurement reference voltage to the first selection pixel through the first data line ( see Figs. 2-3, Fig. 9, para. [0038], [0043], para. [0098]-[0111], para. [0198]-[0203]. The data driving circuit 120 drives the plurality of data lines DL by receiving the image data DATA from the controller 140. Each of the first node N1 and the second node N2 of the driving transistor DRT is initialized with a threshold voltage sensing driving data signal Vdata and a reference voltage Vref (V1=Vdata, V2=Vref) The data driving circuit 120 can supply a data signal for the mobility sensing to the selected real-time sensing subpixel RT Sensing SP in a period in which the real-time sensing process is performed. ), measure a characteristic of the first selection pixel based on a first return signal received through the first return line ( see Fig. 2, para. [0087], para. [0110]-[0111]. The voltage sensed by the analog-to-digital converter ADC can be a voltage in which the characteristic values of the subpixel SP are reflected. The sampling operation is an operation to measure a voltage reflecting the threshold voltage of the driving transistor DRT or a change in the threshold voltage. In the sampling operation, the analog-to-digital converter ADC senses a voltage on the reference voltage line RVL, e.g., the voltage V2 on the second node N2 of the driving transistor DRT. A voltage Vsen sensed by the analog-to-digital converter ADC can be a voltage Vdata-Vth obtained by subtracting the threshold voltage Vth from the data signal Vdata or a voltage Vdata-AVth obtained by subtracting the threshold voltage deviation AVth from the data signal Vdata ), and generate a second data signal corresponding to the first image data based on the characteristic of the first selection pixel ( see [0095]-[0097]. para. [0129]-[0138]. The controller 140 drives the data driving circuit 120 by compensating for image data by reflecting the change in the characteristic values of the subpixel SP calculated by the compensation circuit 220. A data signal Vdata in which the change in the characteristic values of the subpixel SP is reflected can be output through a corresponding data line DL by a digital-to-analog converter DAC. The sensing data output by the analog-to-digital converter ADC can be provided to the compensation circuit 220. The compensation circuit 220 can determine the characteristic values (e.g., threshold voltage and mobility) of the driving transistor DRT in a corresponding subpixel or a change in the characteristic values (e.g., a change in the threshold voltage and a change in the mobility) of the driving transistor DRT based on the sensing data provided by the analog-to-digital converter ADC, and perform a characteristic values compensation process. The compensation circuit 220 can change the image data DATA by the threshold voltage compensation process or the mobility compensation process and provide the changed image data DATA to a corresponding source driving integrated circuit SDIC in the data driving circuit 120. Consequently, the corresponding source driving integrated circuit SDIC converts the data changed by the compensation circuit 220 into a data signal through the digital-to-analog converter DAC, and supplies the data signal to the corresponding subpixel, so that the characteristic values (e.g., the threshold voltage and mobility) of the subpixel are actually compensated for ). Regarding Claim 2 , Park teaches the display device of claim 1. Park further teaches wherein the data driver ( see Figs. 1-2, para. [0044], para. [0086], para. [0138]. The data driving circuit 120 can include one or more source driving integrated circuits (SDICs). A source driving integrated circuit SDIC can include an analog-to-digital converter ADC and a sampling switch SAM. As depicted in figure 2 the source driving integrated circuit SDIC also includes digital-to-analog converter DAC ) includes: a driving circuit configured to generate the second data signal while the display panel displays an image based on the second data signal ( see Fig. 2, DAC, Fig. 9, para. [0137]-[0138], para. [0198]. The compensation circuit 220 can change the image data DATA by the threshold voltage compensation process or the mobility compensation process and provide the changed image data DATA to a corresponding source driving integrated circuit SDIC in the data driving circuit 120.The compensation circuit 220 can change the image data DATA by the threshold voltage compensation process or the mobility compensation process and provide the changed image data DATA to a corresponding source driving integrated circuit SDIC in the data driving circuit 120. Consequently, the corresponding source driving integrated circuit SDIC converts the data changed by the compensation circuit 220 into a data signal through the digital-to-analog converter DAC, and supplies the data signal to the corresponding subpixel, so that the characteristic values (e.g., the threshold voltage and mobility) of the subpixel are actually compensated for. The data driving circuit 120 can supply a data signal for the mobility sensing to the selected real-time sensing subpixel RT Sensing SP in a period in which the real-time sensing process is performed. ); and a sensing circuit configured to receive the first return signal, and generate a pixel characteristic data including the characteristic of the first selection pixel based on the first return signal, while the display device performs a pixel characteristic measurement operation to measure the characteristic of the first selection pixel ( see Fig. 2,ADC, para. [0087], para. [0110]-[0111], para. [0286]. The data driving circuit 120 can include an analog-to-digital converter ADC sensing a voltage on the sensing node. The analog-to-digital converter ADC can sense a voltage on the reference voltage line RVL. The voltage sensed by the analog-to-digital converter ADC can be a voltage in which the characteristic values of the subpixel SP are reflected. The sampling operation is an operation to measure a voltage reflecting the threshold voltage of the driving transistor DRT or a change in the threshold voltage. In the sampling operation, the analog-to-digital converter ADC senses a voltage on the reference voltage line RVL, e.g., the voltage V2 on the second node N2 of the driving transistor DRT. A voltage Vsen sensed by the analog-to-digital converter ADC can be a voltage Vdata-Vth obtained by subtracting the threshold voltage Vth from the data signal Vdata or a voltage Vdata-AVth obtained by subtracting the threshold voltage deviation AVth from the data signal Vdata ). Regarding Claim 9 , Park teaches the display device of claim 2. Park further teaches wherein the display device is configured to perform the pixel characteristic measurement operation during a vertical blank period during which the display panel does not display an image based on the second data signal (see Figs. 5-7, para. [0143]-[0145], para. [0189]-[0194]. The Real-time sensing process can be performed during every blank period BLANK between active periods ACT with respect to a vertical synchronization signal Vsync. The display device according to embodiments can perform the Real-time sensing process in a blank period BLANK between a first active period ACT1 in which an image of a first frame is displayed on the display panel and a second active period ACT2 in which an image of a second frame is displayed on the display panel. The timing controller 140 can select whether or not to perform real-time sensing during a blank period BLANK immediately after an active period ACT of the Nth frame by performing the real-time sensing subpixel selecting process ). Additional Rejection 07-15 AIA Claim 1 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. ( US 20160189625 A1 , hereinafter referenced as Kim) . Regarding Claim 1 , Kim teaches a display device ( see Fig. 3, para. [0075]. Organic light emitting diode display device ) comprising: a display panel ( see Fig. 3, a display panel 116, para. [0076]-[0077] ) including a plurality of pixels ( see Fig. 3, pixels 122, para. [0054] ) connected to a plurality of data lines ( see Fig. 3, para. [0077], para. [0083]. The display panel 116 can include m data lines D1˜Dm ) and a plurality of return lines ( see Fig. 3, para. [0077], para. [0084]. m sensing lines S1˜Sm ); a timing controller ( see Fig. 3, timing controller 124 ) configured to generate first image data corresponding ( see para. [0155]-[0156]. the timing controller 124 can transfer digital video data RGB of an input image to the data driver 120. The timing controller 124 can convert the clock training pattern signal (or EPI clock signal), the control data, the digital video data RGB of the input image and so on into a pair of difference signals and transfer the converted different signal pair to the data driver 120 via the single pair of data lines ) to a first selection pixel connected to a first data line among the plurality of data lines and a first return line among the plurality of return lines ( see Figs. 3-4, para. [0054], para. [0056]. Brightness of the pixel selected by a scan pulse can be controlled on the basis of a gray scale value of digital video data. The active matrix mode selects the pixels by selectively turning-on the thin film transistors. The selected pixel can maintain a light emitting state using a voltage charged into a storage capacitor within the pixel ); and a data driver ( see Fig. 3, para. [0076], para. [0082]. A data driver 120. The data driver 120 can be controlled by data control signals DDC applied from the timing controller 124. Also, the data driver 120 can apply data voltages to the data lines D1˜Dm. Moreover, the data driver 120 can apply a sensing voltage to the sensing lines S1˜Sm ) configured to apply a first data signal corresponding to a measurement reference voltage to the first selection pixel through the first data line ( see Fig. 8, para. [0085], para. [0098], para. [0102]. The data driver 120 can output the data voltage and the sensing voltage and detect the sensing voltage. A sensing voltage Vsen on the data line Di is charged into the first node N1 through the scan switch SW ), measure a characteristic of the first selection pixel based on a first return signal received through the first return line ( see Fig. 8, para. [0102]. Referring to FIGS. 5 and 8, the sensing line Si is electrically connected to an analog-to-digital converter (hereinafter, “ADC”) 250 by a sampling control signal Sam during a threshold voltage detecting interval t3. Then, the voltage on the second node N2 is detected as a threshold voltage and converted into a digital signal shape ), and generate a second data signal corresponding to the first image data based on the characteristic of the first selection pixel ( see Figs. 10-11, Figs.13-15, para. [0102], para. [0107], para. [0116]-[0117], claim 12. The detected threshold voltage Vth is used to generate a compensation data signal Vd which is applied to the data line Di in a driving switch property compensating and organic light emitting diode property sensing mode. As such, the threshold voltage Vth of the driving switch DR can be compensated. The compensation data voltage Vd on the data line Di is charged to the first node N1 through the scan switch SW. The compensation data voltage Vd becomes a sum of a data voltage Vdata and the threshold voltage DR_Vth of the driving switch DR. Also, the reference voltage Vref controlled by the initialization control signal Spre is charged into the second node N2 through the sensing line Si and the sensing switch SEW. Moreover, the storage capacitor Cst is initialized by a voltage difference Vd−Vref. The reference voltage Vref applied to the second node N2 forces the organic light emitting diode OLED not to emit light. The compensation data voltage Vd becomes a sum of a data voltage Vdata and the threshold voltage DR_Vth of the driving switch DR. The compensation data voltage Vd on the data line Di is transferred to the first node N1 via the scan switch SW and enables a current to flow through the driving switch DR which is driven in a source follower mode, as shown in FIG. 13 ) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 10-18 and 20 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 19 would be allowable if rewritten to overcome the objection set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, made of record, singularly or in combination, discloses or fairly suggests the following: Claim 10 : obtaining a first equation by performing a partial differentiation on the first output current with respect to the first data signal; obtaining a second equation by performing an indefinite integration on the first equation with respect to the first data signal; measuring a first pixel current output from the selection pixel in response to the first data signal being applied to the selection pixel based on the second equation In combination with all other claim limitations. Claim 15 : a timing controller configured to… store a pixel characteristic data indicative of a value of a first pixel current output from a first selection pixel among the plurality of pixels in response to a first data signal applied to the first selection pixel, and store an ideal data indicating an ideal co-relationship between the first data signal and the first pixel current; and a data driver configured to generate a first gamma voltage corresponding to the first image data, determine a compensation voltage based on the ideal data and the pixel characteristic data, and generate a second data signal corresponding to the first image data by adding the first gamma voltage and the compensation voltage In combination with all other claim limitations . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IVELISSE MARTINEZ QUILES whose telephone number is (571)270-7618. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IM/Examiner, Art Unit 2626 /TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 6/14/26 Application/Control Number: 19/242,262 Page 2 Art Unit: 2626 Application/Control Number: 19/242,262 Page 3 Art Unit: 2626 Application/Control Number: 19/242,262 Page 4 Art Unit: 2626 Application/Control Number: 19/242,262 Page 5 Art Unit: 2626 Application/Control Number: 19/242,262 Page 6 Art Unit: 2626 Application/Control Number: 19/242,262 Page 7 Art Unit: 2626 Application/Control Number: 19/242,262 Page 8 Art Unit: 2626 Application/Control Number: 19/242,262 Page 9 Art Unit: 2626 Application/Control Number: 19/242,262 Page 10 Art Unit: 2626 Application/Control Number: 19/242,262 Page 11 Art Unit: 2626 Application/Control Number: 19/242,262 Page 12 Art Unit: 2626
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