DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 18 June 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 11-16, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiwada (US 20230138215 A1) in view of Gandhi (US 20120185667 A1).
Referring to claims 1, 14, and 16, taking claim 1 as exemplary, Hiwada teaches
A data storage device comprising: a first memory; a second memory; and a controller ([Hiwada 0036-0037, 0045, Fig. 1] The memory system 3 includes a controller 5, a NAND flash memory 6, and a dynamic random access memory (DRAM) 7. The controller 5 includes a cache 51 and a media control unit 52.) configured to provide a storage virtual memory of a size corresponding to at least a partial storage area of the second memory, ([Hiwada 0035, 0040-0041, 00213, Fig. 1] The processor 21 has a virtual memory function. The memory management unit of the processor 21 translates a virtual memory address used by the application program into a physical memory address. The processor 21 accesses the memory 22 using the physical memory address. The controller 5 executes the management of data stored in the NAND flash memory 6 and the management of blocks included in the NAND flash memory 6. The management of data includes the management of mapping information indicating a correspondence relationship between each of the logical addresses (i.e. virtual memory) and each of the physical addresses of the NAND flash memory 6. With the use of the address translation table, the controller 5 manages mapping between each of the logical addresses and each of the physical addresses in units of a certain management size. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. The logical address is an address used by the host 2 (processor 21) to access the memory system 3. The physical address is an address indicating a storage location (physical storage location) included in a physical storage area included in the NAND flash memory 6. configuration in which a logical address is translated into virtual location information such as an offset within the region by first-stage address translation using the page table 71, and the virtual location information such as the offset within the region is translated into an actual physical address) and configured to process a page request from a host device for the first memory using an … page table, ([Hiwada 0038, 0040-0041, 0054-0055, Fig. 1] Each of the blocks includes a plurality of physical pages. The individual physical pages include a plurality of memory cells connected to the same word line. The individual physical pages are a unit of a data program operation and a data read operation. In a data read operation within the page, the NAND flash memory 6 can output only a part of data of one physical page size which are read from one physical page, to the controller 5. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. The logical address is an address used by the host 2 (processor 21) to access the memory system 3. The physical address is an address indicating a storage location (physical storage location) included in a physical storage area included in the NAND flash memory 6.) which includes mapping information between a logical address from the storage virtual memory and a physical address of the first memory ([Hiwada 0041, 0054-0055, Fig. 4] The management of data includes the management of mapping information indicating a correspondence relationship between each of the logical addresses and each of the physical addresses of the NAND flash memory 6. With the use of the address translation table, the controller 5 manages mapping between each of the logical addresses and each of the physical addresses in units of a certain management size. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. the page table 71 manages mapping between each of the logical addresses included in the logical address space and each of the physical addresses included in the physical address space in units of a first size corresponding to granularity (access granularity) of data read/write-accessed by the host. In the following, the case in which the access granularity is 64 bytes (64 B) and the page table 71 manages mapping between each of the logical addresses and each of the physical addresses in units of 64 B will be mainly described. In the case in which the page table 71 manages mapping between each of the logical addresses and each of the physical addresses in units of 64 B, the address translation unit of the page table 71 is 64 B. The address translation unit of the page table 71 is also referred to as a page.).
Hiwada does not explicitly disclose inverted page table. Hiwada does disclose page table ([Hiwada 0041, 0053, Fig. 4]).
Gandhi teaches inverted page table ([Gandhi 0004] The MMU comprises a lookup-table, in the form of a translation lookaside buffer, a page table, an inverted page-table, a hash-table, or the like, to associate a range of addresses in the virtual address space with a page-table-entry.).
Hiwada and Gandhi are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hiwada and Gandhi before him or her to modify the page table of Hiwada to include the inverted page table of Gandhi, thereafter the page table is connected to inverted page table. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the page table to be interchanged with the inverted page table as suggested by Gandhi. It is known to simple substitute one known element for another to obtain predictable results. Therefore, it would have been obvious to combine Hiwada with Gandhi to obtain the invention as specified in the instant application claims.
With regards to the non-exemplary limitations of claims 14 and 16, Hiwada teaches second memory, which is distinguished from the first memory ([Hiwada 0036-0037, 0045, Fig. 1] The memory system 3 includes a controller 5, a NAND flash memory 6, and a dynamic random access memory (DRAM) 7. The controller 5 includes a cache 51 and a media control unit 52.) and second memory, which is distinguished from the first memory, as a physical memory ([Hiwada 0036-0037, 0045, Fig. 1] The memory system 3 includes a controller 5, a NAND flash memory 6, and a dynamic random access memory (DRAM) 7. The controller 5 includes a cache 51 and a media control unit 52.).
Referring to claim 2, Hiwada in view of Gandhi teaches
The data storage device according to claim 1, wherein the controller processes the page request by receiving a virtual address from the host device, checking a logical address from the storage virtual memory mapped to the virtual address, and checking a physical address of the first memory mapped to the logical address ([Hiwada 0029, 0037, 0041, Fig. 1] In response to receiving a write access request and first write data from the host, the write access request specifying a logical address of the first write data, the controller identifies a bank to which the logical address of the first write data belongs, and writes the first write data to a write buffer corresponding to the identified bank among the 2.sup.N write buffers. After a total size of write data stored in the write buffer, including the first write data, becomes equal to or larger than a threshold size, the controller writes the write data including the first write data to a first region among the 2.sup.N regions, the first region corresponding to the identified bank. Each of the plurality of entries stores, as the physical address, location information indicating one of a plurality of first storage locations, the plurality of first storage locations being included in one region among the 2.sup.N regions, the one region corresponding to one bank to which a logical address corresponding to the entry belongs. Each of the plurality of entries does not store location information for identifying the one region. the controller 5 executes communication with the processor 21 of the host 2 through the memory bus 4. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. The logical address is an address used by the host 2 (processor 21) to access the memory system 3. The physical address is an address indicating a storage location (physical storage location) included in a physical storage area included in the NAND flash memory 6.).
Referring to claim 3, Hiwada in view of Gandhi teaches
The data storage device according to claim 1, wherein the controller processes the page request by using at least one page table, which includes mapping information between a virtual address from the host device and the logical address according to the storage virtual memory and the inverted page table ([Hiwada 0041, 0054-0055, Fig. 4] The management of data includes the management of mapping information indicating a correspondence relationship between each of the logical addresses and each of the physical addresses of the NAND flash memory 6. With the use of the address translation table, the controller 5 manages mapping between each of the logical addresses and each of the physical addresses in units of a certain management size. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. the page table 71 manages mapping between each of the logical addresses included in the logical address space and each of the physical addresses included in the physical address space in units of a first size corresponding to granularity (access granularity) of data read/write-accessed by the host. In the following, the case in which the access granularity is 64 bytes (64 B) and the page table 71 manages mapping between each of the logical addresses and each of the physical addresses in units of 64 B will be mainly described. In the case in which the page table 71 manages mapping between each of the logical addresses and each of the physical addresses in units of 64 B, the address translation unit of the page table 71 is 64 B. The address translation unit of the page table 71 is also referred to as a page.).
Referring to claim 11, Hiwada in view of Gandhi teaches
The data storage device according to claim 1, wherein the controller receives the page request, which is transmitted by the host device, and the host device recognizes a physical memory corresponding to the size of the storage virtual memory ([Hiwada 0029, 0037, 0041, Fig. 1] the controller 5 executes communication with the processor 21 of the host 2 through the memory bus 4. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. The logical address is an address used by the host 2 (processor 21) to access the memory system 3. The physical address is an address indicating a storage location (physical storage location) included in a physical storage area included in the NAND flash memory 6.).
Referring to claim 12, Hiwada in view of Gandhi teaches
The data storage device according to claim 1, wherein the controller receives the page request, which is transmitted by the host device, and the host device recognizes a physical memory corresponding to a size obtained by summing the size of the first memory and the size of the storage virtual memory ([Hiwada 0029, 0037, 0041, Fig. 1] In response to receiving a write access request and first write data from the host, the write access request specifying a logical address of the first write data, the controller identifies a bank to which the logical address of the first write data belongs, and writes the first write data to a write buffer corresponding to the identified bank among the 2.sup.N write buffers. After a total size of write data stored in the write buffer, including the first write data, becomes equal to or larger than a threshold size, the controller writes the write data including the first write data to a first region among the 2.sup.N regions, the first region corresponding to the identified bank. Each of the plurality of entries stores, as the physical address, location information indicating one of a plurality of first storage locations, the plurality of first storage locations being included in one region among the 2.sup.N regions, the one region corresponding to one bank to which a logical address corresponding to the entry belongs. Each of the plurality of entries does not store location information for identifying the one region. the controller 5 executes communication with the processor 21 of the host 2 through the memory bus 4. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. The logical address is an address used by the host 2 (processor 21) to access the memory system 3. The physical address is an address indicating a storage location (physical storage location) included in a physical storage area included in the NAND flash memory 6.).
Referring to claim 13, Hiwada in view of Gandhi teaches
The data storage device according to claim 1, wherein the size of the second memory is larger than the size of the first memory ([Hiwada 0039, 0065, 0099, 0112-0113, Fig. 1] The DRAM 7 is a random access memory. The DRAM 7 is a volatile memory that allows high speed access higher than the NAND flash memory 6 does. For example, in the case in which the capacity allocated to the 2.sup.N banks is 512 GB in the physical storage area of the NAND flash memory 6, each of the 2.sup.N regions has a capacity of 512 GB/2.sup.N . dividing the logical address space into 2.sup.N banks, it is possible to reduce the capacity of the entire DRAM 7 necessary to store the page table 71 and the write buffer 72. N may be set to a natural number of ten or more. In the case in which N is ten or more, it is possible to reduce the capacity of the page table 71 by 5 GB or more. The reduction amount of 5 GB is a reduction amount that is ten times the reduction amount of 0.5 GB of the page table 71 in the case in which N is 1. In the case in which N is 10, the number of banks is 1024, and thus the total capacity of the write buffer 72 is 32 MB (=32 KB×1024). The total capacity of 32 MB of the write buffer 72 is about 30 times “write size×parallel write number”. Therefore, by setting N to ten or more, it is possible to sufficiently reduce the capacity of the entire DRAM 7 that has to store the page table 71 and the write buffer 72 as compared with the case in which the logical address space is not divided.).
Referring to claims 15 and 20, taking claim 15 as exemplary, Hiwada in view of Gandhi teaches
The data storage device according to claim 14, wherein the second memory is located outside of the data storage device ([Hiwada 0036-0037, 0045, Fig. 1] The memory system 3 includes a controller 5, a NAND flash memory 6, and a dynamic random access memory (DRAM) 7. The controller 5 includes a cache 51 and a media control unit 52.).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claim 19, Hiwada in view of Gandhi teaches
The computing system according to claim 16, wherein the host device recognizes the size of the first memory and the size of the storage virtual memory as the physical memory ([Hiwada 0029, 0037, 0041, Fig. 1] In response to receiving a write access request and first write data from the host, the write access request specifying a logical address of the first write data, the controller identifies a bank to which the logical address of the first write data belongs, and writes the first write data to a write buffer corresponding to the identified bank among the 2.sup.N write buffers. After a total size of write data stored in the write buffer, including the first write data, becomes equal to or larger than a threshold size, the controller writes the write data including the first write data to a first region among the 2.sup.N regions, the first region corresponding to the identified bank. Each of the plurality of entries stores, as the physical address, location information indicating one of a plurality of first storage locations, the plurality of first storage locations being included in one region among the 2.sup.N regions, the one region corresponding to one bank to which a logical address corresponding to the entry belongs. Each of the plurality of entries does not store location information for identifying the one region. the controller 5 executes communication with the processor 21 of the host 2 through the memory bus 4. The address translation table is also referred to as a logical-to-physical address translation table (L2P table) or a page table. The logical address is an address used by the host 2 (processor 21) to access the memory system 3. The physical address is an address indicating a storage location (physical storage location) included in a physical storage area included in the NAND flash memory 6.).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiwada (US 20230138215 A1) in view of Gandhi (US 20120185667 A1) as applied to claim 16 above, and further in view of Ingalls (US 20230195647 A1).
Referring to claim 17, Hiwada in view of Gandhi teaches
The computing system according to claim 16 ([see above]).
Hiwada in view of Gandhi teaches does not explicitly disclose wherein when a miss occurs in the data processing using the inverted page table, the host device performs a fault handling operation using a hypervisor fault handler.
Ingalls wherein when a miss occurs in the data processing using the inverted page table, the host device performs a fault handling operation using a hypervisor fault handler ([Ingalls 0013, 0031, Figs. 1, 2] a hypervisor manages a physical computing device (e.g., a system on a chip (SOC)) to provide an environment in which one or more virtual machines run and are able to execute their own software. the hypervisor may have a page table for mapping its virtual addresses to physical addresses of memory in the physical computing device. A virtual machine running over the hypervisor may maintain its own page table for mapping its virtual addresses, which may be call guest virtual addresses, to its own simulated physical addresses, which may be called guest physical addresses. The system 200 includes a load/store unit 210, a translation lookaside buffer 212, an exception update circuitry 214, a hypervisor trap control status register 216, and a fault handling circuitry 220. The fault handling circuitry 220 includes a sidecar data store 222 and a page table walk circuitry 224.).
Hiwada, Gandhi, and Ingalls are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hiwada, Gandhi, and Ingalls before him or her to modify the system of Hiwada and Gandhi to include the hypervisor and fault handling of Ingalls, thereafter the system is connected to hypervisor and fault handling. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system to allow for improved performance by managing faults suggested by Ingalls. It is known to simple substitute one known element for another to obtain predictable results. Therefore, it would have been obvious to combine Hiwada and Gandhi with Ingalls to obtain the invention as specified in the instant application claims.
Referring to claim 18, Hiwada in view of Gandhi teaches
The computing system according to claim 17([see above]).
Hiwada in view of Gandhi teaches does not explicitly disclose wherein when a miss occurs in a page request for the physical memory, the host device performs a fault handling operation using a page fault handler.
Ingalls teaches wherein when a miss occurs in a page request for the physical memory, the host device performs a fault handling operation using a page fault handler ([Ingalls 0018, 0029 Fig. 1] The fault handling circuitry 180 may be configured to, responsive to a fault condition on a hit in the translation lookaside buffer 170 for a first address translation request from the processor pipeline for a first guest virtual address, invoke a single-stage page table walk with the first guest virtual address to obtain a first guest physical address; and store the first guest physical address with the first guest virtual address in the sidecar data store 182. The fault handling circuitry 180 may also be configured to cause the translation lookaside buffer 170 to return a miss to the processor pipeline 130 in response the first address translation request rather than a hit with the fault condition. The fault handling circuitry 180 may be configured to, cause the translation lookaside buffer 170 to return a miss to the processor pipeline 130 in response the first address translation request rather than a hit with the fault condition. Sending a miss may cause the processor pipeline 130 to retry the first address translation request later and give the fault handling circuitry 180 some time to complete a single-stage page table walk to make the first guest physical address associated with the first address translation request available in the data store 182. The processor pipeline 130 may be configured to, in response to the miss).
Hiwada, Gandhi, and Ingalls are analogous art because they are from the same field of endeavor in memory devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Hiwada, Gandhi, and Ingalls before him or her to modify the system of Hiwada and Gandhi to include the hypervisor and fault handling of Ingalls, thereafter the system is connected to hypervisor and fault handling. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system to allow for improved performance by managing faults suggested by Ingalls. It is known to simple substitute one known element for another to obtain predictable results. Therefore, it would have been obvious to combine Hiwada and Gandhi with Ingalls to obtain the invention as specified in the instant application claims.
Allowable Subject Matter
Claims 4-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding page tables.
US 20210081326 A1
US 20130250686 A1
US 20120331265 A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
Prosecution Insights