Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on 6/18/2025. Claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/26/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-20 are objected to because of the following informalities: Claim 1, line 8 recites “sent by a current GPU”. Similar issues present in Claim 7, line 5, Claim 12, line 13, Claim 18, line 10, and Claim 18, line 10 also recites “sent by a current GPU”. Claims 2-6, 13-17, 19, and 20 are objected to due to their dependency to the objected independent claims recited above. The term “GPU” should be spelt out at least once. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over Abts (USPGPUB No. 2025/0139439 A1) in view of NAEIMI et al. (USPGPUB No. 2023/0300063 B1, hereinafter referred to as NAEIMI).
As per claim 1, Abts discloses a method for data processing {“one or more slices 2001A-2001N includes one or more [data processing methods] ray tracing units to compute ray tracing operations”, see Figs. 20a-20b [0331] 1st sentence}, which is applied to a bottom-layer switch in a multi-layer switch {“[multi-layer link fabric sublayer that is attached to a switch and a GPU-GPU bridge” (see Figs. 20a-20b [0336], 1st sentence) as a switch/layers entering or functioning as “one or more inputs from sources external to neuromorphic processor 2700” (see Fig. 27, [0415], 1st sentence}, wherein the multi-layer switch is configured to complete a target operation {“accelerator(s) 1214 could be used for targeted workloads”, see Fig. 12c, [0174] last two sentences}, the method receiving a plurality of in-network computing requests {“access locally to allow for efficient request interleaving among partition units”, see Fig. 22a, [0375] last two sentences} sent by a top-layer switch {“PCIe switches 1282), and/or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with high-speed interconnects”, see Fig. 12D [0239], 3RD sentence} in the multi-layer switch {“least one embodiment, [top-layer] host interface switch 2304”, see Fig. 23 [0387], 2nd sentence};
wherein the plurality of in-network computing requests correspond to the plurality of stage operations {“[plurality of stage operations each] captures gradient data indicating a differential contribution of every input, and each layer or other processors exchanges gradients [in-network”, see Fig. 2 [0066] last two sentences}, and the plurality of in-network computing requests {“In at least one embodiment, [in-network] local requests from a GPU 1710 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1720”, see Fig. 17F, [0312] 2nd sentence} are sent by a current GPU to the top-layer switch {“one or more processes of system 100 are performed by any suitable processing system or [current GPU] unit (e.g., graphics processing unit (GPU), general-purpose GPU (GPGPU”, see Fig. 2 [0067], 3RD sentence};
executing the plurality of stage operations in parallel {“provides a beneficial operating environment for GPU offload [in parallel]”, [0310], 2nd sentence} for a plurality of GPUs in a current subgroup {“selection of [current subgroup] GPU bias”, see Fig. 17f [0311] 1st sentence} based on the plurality of in-network computing requests {“ensures cache coherence [requests] between caches of one or more host processors (e.g., 1705)”, see Fig. 17F, [0309], 1st sentence};
wherein a target group {“bias table entry associated with each access to a GPU attached memory 1720 is accessed”, see Fig. 17f [0312], 1st sentence} to which the current GPU belongs is divided into a plurality of subgroups {“to perform graphics processing, scheduler 2210 can be configured to divide a processing workload into approximately equal sized tasks … to multiple clusters 2214A-2214N”, see Fig. 22a, [0361], 1st sentence}, and the current subgroup is a subgroup corresponding to the bottom-layer switch among the plurality of subgroups {“biasing techniques indicating physical memories in which certain types of data should be stored” (see Fig. 17f [0309] 1st sentence) “requests directed to a GPU-biased page may be forwarded to a GPU 1710” including a GPU in the layer switch as claimed (see Fig. 17F, [0312], last three sentences}.
Abts does not appear to explicitly disclose comprises a plurality of stage operations;
wherein the plurality of in-network computing requests correspond to the plurality of stage operations one-to-one, and the plurality of in-network computing requests are sent by a current GPU to the top-layer switch;
However, NAEIMI discloses comprises a plurality of stage operations {“the [match-action unit] MAUs includes a sequence of stages,”, see Fig. 9a [0072] 1st sentence};
wherein the plurality of in-network computing requests {“Packet 200 can be implemented as RDMA over Converged Ethernet (RoCE) v2 consistent packet [in-network computing request(s)”, see Fig. 2, [0028], 1st sentence}, correspond to the plurality of stage operations one-to-one {“each stage including one or more match tables and an action engine. A match table can include a set of match entries against which the [in-network request(s)] packet header fields are matched”, see Figs. 8B, 9a, [0072], 2nd sentence}, and the plurality of in-network computing requests {“multiple parameter servers to leverage the parallel computation of, e.g., graphics processing units (GPUs)”, [0003], 3rd sentence} are sent by a current GPU to the top-layer switch {“network interface 1050 are part of an Infrastructure Processing Unit (IPU) or data processing unit (DPU) or utilized by an IPU or DPU. An xPU can refer at least to an IPU, DPU, [current] GPU, GPGPU, or other processing units” as claimed, see Fig. 10, [0090], 1st sentence}.
Abts and NAEIMI are analogous because they are from the same field of endeavor, networked device managing communication stream(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Abts and NAEMI before him or her, to modify Abts {“[multi-layer link fabric sublayer that is attached to a switch and a GPU-GPU bridge” (see Figs. 20a-20b [0336], 1st sentence) in concert with “one or more inputs from sources external to neuromorphic processor 2700” (see Fig. 27, [0415], 1st sentence) incorporating NAEIMI “the [match-action unit] MAUs 924” (see Fig. 9a [0071] 1st sentence).
The suggestion/motivation for doing so would have been to implement RDMA RC mode can benefit from bandwidth reduction by truncating Reduce Scatter (or Reduce Scatter part of AllReduce) packets and sending header-only packets to the end point destination ports (NAEIMI [0054], 2nd sentence).
Therefore, it would have been obvious to combine NAEIMI with Abts to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Abts discloses wherein, the plurality of in-network computing requests are received by a current uplink port {“uop schedulers 2502, 2504, 2506 arbitrate for dispatch ports to schedule uops for execution”, see Fig. 25, [0399], last sentence}; the current uplink port corresponds to a current top-layer port {“one or more [current top layer] ports, one or more shift and/or shifter units”, see Fig. 25, [0405], 2nd sentence}, and the current top-layer port is a port on the top-layer switch connected to the current GPU {“PCIe switches 1282), and/or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with high-speed interconnects”, see Fig. 12D [0239], 3RD sentence};
the plurality of stage operations comprise: a first stage operation and a second stage operation {“each layer or other processors exchanges gradients [first or second stage] using an AllReduce operation”, see Fig. 1, [0066] last sentence};
the executing the plurality of stage operations in parallel {“provides a beneficial operating environment for GPU offload [in parallel]”, [0310], 2nd sentence} for a plurality of GPUs in a current subgroup {“selection of [current subgroup] GPU bias”, see Fig. 17f [0311] 1st sentence} based on the plurality of in-network computing requests {“ensures cache coherence [requests] between caches of one or more host processors (e.g., 1705)”, see Fig. 17F, [0309], 1st sentence} comprises:
determining the plurality of GPUs {“selection of [current subgroup] GPU bias”, see Fig. 17f [0311] 1st sentence} based on each in-network computing request at the current uplink port {“ensures cache coherence [requests] between caches of one or more host processors (e.g., 1705)”, see Fig. 17F, [0309], 1st sentence};
in the first stage operation, receiving a first data to be processed sent by each GPU {“a processor captures [receiving a first data] gradient data indicating a differential contribution of every input”, see Fig. 1 [0066], last sentence} of the plurality of GPUs {;
obtaining initial result data based on the first data to be processed {“to communicate each [initial result] gradient to other parallel processors in a distributed training system, such as system 100”, see Fig. 1, [0066], last sentence};
sending the initial result data to the top-layer switch {“corresponding surrogate [initial result data] neural network gradient values and/or otherwise perform operations discussed herein”, see Figs. 1-4 [0069], last sentence};
in the second stage operation {“each layer or other processors exchanges gradients [first or second stage] using an AllReduce operation” (see Fig. 1, [0066] last sentence) producing result data per stage.}, receiving a second target result data sent by the top-layer switch {“to communicate each [second target result] gradient to other parallel processors in a distributed training system, such as system 100”, see Fig. 1, [0066], last sentence};
sending the second target result data to each of the GPUs {“GPUs, in an embodiment, one or more APIs 810 provide one or more API functions 812 to cause 816 replacement of one or more corrupt neural network gradient values or network packets with one or more [received] corresponding surrogate neural network gradient values”, see Figs. 1-7, [0105], 1st sentence};
wherein the first data to be processed and the second target result data are received in parallel {“n API 810 is an API to facilitate parallel computing” to the respective first data and second target result data as claimed, see Fig. 8, [0103], 1st sentence};
and/or, the initial result data and the second target result data are sent in parallel {“GPU(s) 1208 may be programmable and may be efficient for parallel workloads [including result data and target result data”, see Fig. 12C, [0168] 1st sentence}.
As per claim 3, the rejection of claim 2 is incorporated and Abts discloses wherein, each in-network computing request comprises a current group identifier of the target group {“[current group identifier] graphics acceleration module type describes a targeted acceleration function for a system call [request]”, see Figs. 17E and 17F [0303], 2nd sentence};
the determining the plurality of GPUs {“selection of [current subgroup] GPU bias”, see Fig. 17f [0311] 1st sentence} based on each in-network request comprises {“ensures cache coherence [requests] between caches of one or more host processors (e.g., 1705)”, see Fig. 17F, [0309], 1st sentence}:
determining subgroup members corresponding to the current group identifier {“[determining] driven by a bias tracker data structure”, see Fig. 17f, [0311], 1st sentence} based on a pre-established correspondence between group identifiers {“create a [pre-established correspondence] multi-GPU cluster to”, see Fig. 20B, [0341], 2nd sentence} and subgroup members as the plurality of GPUs {“enables communication and synchronization between multiple instances of GPGPU 2030”, see Fig. 20a, [0344] sentence}.
As per claim 4, the rejection of claim 2 is incorporated and NAEIMI discloses wherein, the target operation is an AllReduce operation {“Other operations can be performed such as Allreduce”, see Figs. 2 and 3, [0038], last sentence};
the first stage operation comprises: a ReduceScatter stage operation {“a combination of ReduceScatter and Allgather”, see Figs. 2 and 3, [0038], last sentence};
the first data to be processed comprises: original data on each of the GPUs {“summation of packet data with other packet data from other workers”, see Fig. 3, [0041], 2nd sentence};
the initial result data comprises: initial local reduction data {“Data dissemination 306 can perform [local/remote] distribution of data”, see Fig. 3, [0042], 1st sentence} corresponding to the obtaining initial result data based on the first data to be processed comprises {“can store a [initial] result of the computation into a memory slot identified…”, see Fig. 8a, [0063], 5th sentence}:
performing reduction processing on the original data {“[original data] in accordance with Allreduce, ReduceScatter, or Allgather operations.”, see Fig. 3, [0042] } on each of the GPUs to obtain the initial local reduction data {“network interface device can insert or replace the payload of the dummy packet with the stored payload”, see Fig. 1, [0019], last sentence}.
As per claim 5, the rejection of claim 4 is incorporated and NAEIMI discloses wherein, the receiving the first data to be processed sent by each GPU of the plurality of GPUs comprises {“parameter servers to leverage the parallel computation of, e.g.,[plurality of GPUs] graphics processing units (GPUs) located at a parameter server”, see Fig. 1, [0003], 3RD sentence}:
sending a load request to each of the GPUs {“filler data can be loaded into a packet processing pipeline”, see Fig. 7 [0061], 2nd sentence}, wherein the load request is configured to trigger each of the GPUs to send original data {“Pipeline can replace filler data” as triggered, see Fig. 7 [0061] };
receiving a load response sent by each of the GPUs {“Pipeline can insert one or more packet [load response] checksum or CRC values”, see Fig. 7 [0061] last sentence}, wherein the load response comprises the original data on each of the GPUs {“summation of packet data with other packet data from other [each of the GPU] workers”, see Fig. 3, [0041], 2nd sentence}.
As per claim 6, the rejection of claim 2 is incorporated and NAEIMI discloses wherein, the target operation is an AllReduce operation {“Other operations can be performed such as Allreduce”, see Figs. 2 and 3, [0038], last sentence};
the second stage operation comprises: an AllGather stage operation {“host can send header-only packets in connection with AllGather (or the AllGather part of AllReduce) operations”, see Fig. 5, [0054]};
the second target result data comprises: global reduction data {“insertion of [global reduction] computed result data into packets to be sent to workers”, see Fig. 10, [0087], 1st sentence};
the sending the second target result data to each of the GPUs comprises {“include a [second target result data] payload and transmit the expanded packets to the end point destination”, see Fig. 5, [0054] }:
sending a storage request to each of the GPUs {“Memory 968 can be configured to store packets”, see Fig. 9b, [0078], 1st sentence}, wherein the storage request comprises the global reduction data {“generates a display based on data stored in memory 1030 or based on operations executed by processor 1010 or both.”, see Figs. 9c and 10, [0083], last sentence}.
Referring to claim 7-11 are method claims reciting claim functional language corresponding to the method claim of claims 1-6, respectively, thereby rejected under the same rationale as claims 1-6 above, inter alia, Abts discloses which is applied to a top-layer switch {“PCIe switches 1282), and/or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with high-speed interconnects”, see Fig. 12D [0239], 3RD sentence} in a multi-layer switch {“least one embodiment, [top-layer] host interface switch 2304”, see Fig. 23 [0387], 2nd sentence}.
Referring to claim 12-17 are electronic device claims reciting claim functional language corresponding to the method claim of claims 1-6, respectively, thereby rejected under the same rationale as claims 1-6 above.
Referring to claim 18-20 are non-transitory computer readable storage medium device claims reciting claim functional language corresponding to the method claim of claims 1-6, respectively, thereby rejected under the same rationale as claims 1-6 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “current GPU”, “data processing”, or “target group is divided into a plurality of subgroups”: US 12693985 B2, US 12335137 B2, US 20250139439 A1, US 20250141587 A1, US 20230300063 A1, US 20230177328 A1, US 20220060418 A1, US 20220014555 A1, US 10728172 B2, and US 20190205745 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
