DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are present in this application. Claims 1-20 are pending in this office action.
Drawings
The drawings received on 19 June 2025 are accepted by the Examiner.
This Office Action is Non-Final
Claims rejection 35 U.S.C. 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-14 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because claims 1-14 recite “A pipeline data processing stack” which is not at least one of the four categories of patent eligible subject matter recited in 35 U.S.C. 101 (process, machine, manufacture, or composition of matter). Therefore the claims are patent ineligible.
Claims 15-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Step 1 (All Claims)
According to the first part of the analysis, in the instant case claims 15-19 are directed to a method; Claim 20 is directed to a program product. Thus, each of the claims falls within one of the four statutory categories (i.e. process, machine, manufacture, or composition of matter).
Step 2A, Prong 1 (Claim 15)
Regarding claims 15, and 20, the following limitation is an abstract idea:
Exemplary claim 15 recites "…transform visual data received from a first data source over a data transceiver interface…; transform machine learning data received from a second data source over the data transceiver interface". The limitation is merely transforming input data to output data, which can be mentally performed.
Step 2A Prong 2 (Claims 15, and 20)
Claim 15 recites the additional elements of first compute unit, second compute unit; processing unit; transceiver interface; aa structure of processing units. These are high-level recitation of a generic computer components and represents mere instructions to apply on a computer as in MPEP 2106.05(f), which does not provide integration into a practical application.
Viewing the additional limitations together and the claim as a whole, nothing provides integration into a practical application.
Step 2B (Claims 15, and 20)
The claim is directed to data gathering, data manipulation and producing a result using a computer technology as a tool and is identified as insignificant extra-solution activity above when re-evaluated this element is well-understood, routine, and conventional as evidenced by the court cases in MPEP 2106.05(d)(II), "i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); … OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);" and thus remains insignificant extra-solution activity that does not provide significantly more. Furthermore, mere implementation using a computer and field of use are carried over and does not provide significantly more.
Therefore, looking at the claim as a whole does not change this conclusion and the claim is ineligible
The dependent claims have been considered and do not appear to provide additional requirements that overcome the claims from being abstract or providing additional elements that are sufficient to amount to significantly more than the judicial exception
Claims rejection 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-9, 11-12 and 15-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Groen et al. (US 7885320 B1) in view of Das et al. (US 20180329644 A1) further in view Hu el. (US 20230244525 A1).
Regarding claims 1, 15 and 20 Groen discloses a first compute unit comprising first processing units configurable to transform … received from a first data source over a data transceiver interface (see Groen Col. 1, lines 36-42, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information. After processing the data, the parallel data must be converted back to serial data for transmission without loss); and
a second compute unit comprising second processing units configurable to transform … data received from a second data source over the data transceiver interface (see Groen Col. 13, lines 44-50, The transceiver may then determine at least one output port for providing outgoing data streams (step 286). The transceiver may then provide each input data stream to the at least one output port based upon a corresponding recovered clock (step 288)); wherein the data transceiver interface is operable to transmit the first and second relative output data according to scheduling from the graph scheduler (see Groen Col. 13, lines 45-50, The method of providing the outgoing data streams to the at least one output port comprises, in one embodiment of the invention, providing the outgoing data streams to a number of output ports that corresponds to a number of input data streams wherein the method further includes determining, for each input data stream, an output port and providing the input data streams to the determined output ports at a corresponding recovered clock of the corresponding plurality of recovered clocks (step 290).
Das expressly disclose pipeline data processing stack comprising a first compute unit and a second compute unit (see Das Abstract, A data pipeline architecture is integrated with an analytics processing stack. The data pipeline architecture may receive incoming data streams from multiple diverse endpoint systems);
wherein the first compute unit comprises a first configuration unit operable in electronic communication and a second compute unit comprising second processing units configurable to transform (see Das paragraph [0065], the “transformer:” specifier directs the DPA 114 to use functions for transformation, e.g., stand-alone functions available in pre-defined library. Two examples are the date-transformer function and the epoch-transformer function specified to act on specific fields of the incoming data stream; see Das paragraph [0065], The converter interface circuitry 1330 may be disposed within the integration circuitry 116 of the DPA 1300. The converter interface circuitry 1330 may perform a classification on the input streams (1404). The classification may include determining an input stream type for multiple input streams received from multiple endpoints. The input stream types may include, structured data streams, natural language data streams, media streams, or other input stream types).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Das into the method of Groen to have pipeline data processing stack. Here, combining Das with Groen, which are both related to data processing improves Groen by providing improvement in cloud system architectures, including data processing pipelines, that will drive the further development and implementation of functionality into the cloud (see Das paragraph [0003]).
Hu expressly discloses a graph scheduler to configure operation (see Hu paragraph [0026],a graph tracer 210 traces the utilization of the input model executions of the browser APIs within the browser renderer process and constructs a compute graph of the processing pipeline. The graph tracer 210 is instantiated by processor circuitry executing compute graph tracer instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 5. Graph scheduler circuitry 220 communicates information generated from the compute graph to XPU selection service circuitry 234) and
processing unit linkage of the first compute unit to transform visual input data to first relative output data according to scheduling from the graph scheduler (see Hu paragraph [0026],a graph tracer 210 traces the utilization of the input model executions of the browser APIs within the browser renderer process and constructs a compute graph of the processing pipeline. The graph tracer 210 is instantiated by processor circuitry executing compute graph tracer instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 5. Graph scheduler circuitry 220 communicates information generated from the compute graph to XPU selection service circuitry 234);
wherein the second compute unit comprises a second configuration unit operable in electronic communication with the graph scheduler to configure operation and processing unit linkage of the second compute unit to transform machine learning input data to second relative output data according to scheduling from the graph scheduler (see Hu paragraph [0026],a graph tracer 210 traces the utilization of the input model executions of the browser APIs within the browser renderer process and constructs a compute graph of the processing pipeline. The graph tracer 210 is instantiated by processor circuitry executing compute graph tracer instructions and/or configured to perform operations such as those represented by the flowchart of FIG. 5. Graph scheduler circuitry 220 communicates information generated from the compute graph to XPU selection service circuitry 234).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Hu into the method of Groen to have pipeline data processing stack. Here, combining Hu with Groen, which are both related to data processing improves Groen by providing improvement in cloud system architectures, including data processing pipelines, that will drive the further development and implementation of functionality into the cloud (see Hu paragraph [0003]).
Regarding claims 2 and 16, Groen discloses wherein at least one transform comprises a change in data content between input data and output data (see Groen Col. 1, lines 35-40, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information. After processing the data, the parallel data must be converted back to serial data for transmission without loss).
Regarding claims 3 and17 Groen discloses wherein at least one transform comprises a change in data format between input data and output data (see Groen Col. 1, lines 35-40, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information. After processing the data, the parallel data must be converted back to serial data for transmission without loss).
Regarding claim 4 Groen discloses wherein at least one of the first and the second configuration units is operable to configure an instance of the first or the second processing units to operate sequentially (see Groen Col. 12, lines 45-50, a sequential phased locked loop system enables the receiver section to readily capture the inbound serial data 52. As one of average skill in the art will appreciate, clock data recovery block 226 may use single-ended signals or differential signals).
Regarding claim 5 Groen discloses, wherein at least one of the first and the second configuration units is operable to configure an instance of the first or the second processing units to operate in parallel (see Groen Col. 1, lines 35-40, however, the system components and end user devices may process data in a parallel manner. As such, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information. After processing the data, the parallel data must be converted back to serial data for transmission without loss).
Regarding claim 8 Groen discloses, wherein at least one transform comprises filtering the data (see Groen Col. 7, lines 40-45, The phase detection module 114 provides the current signal to the loop filter 116, which converts it into a control voltage that controls the output frequency of the voltage controlled oscillator 118).
Regarding claim 9 Groen discloses wherein at least one transform comprises converting data to a specified format (see Groen Col. 13, lines 1-6, input data stream according to a first protocol and converting the high data rate input data stream to a second protocol based on the recovered clock (step 258)).
Regarding claim 11 Groen discloses wherein at least one transform comprises synchronizing timing-sensitive data (see Groen Col. 9, lines 55-60, the invention includes performing functions that are synchronized in time with the data for which the function is being performed. By separating functionality from a system clock or reference clock, and by synchronizing the functionality with a clock within a serial data transmission, a need for large buffers and the possibility of buffer overflows/underflows due to mismatches in the reference clock and the data stream rate is avoided).
Regarding claim 12 Groen discloses wherein transmitting the first and second relative output data comprises providing the first and second relative output data to a further structure of processing units configurable to process the first and second relative output data (see Groen Col. 13, lines 45-54, The method of providing the outgoing data streams to the at least one output port comprises, in one embodiment of the invention, providing the outgoing data streams to a number of output ports that corresponds to a number of input data streams wherein the method further includes determining, for each input data stream, an output port and providing the input data streams to the determined output ports at a corresponding recovered clock of the corresponding plurality of recovered clocks (step 290).
Claims 6-7 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Groen et al. (US 7885320 B1) in view of Das et al. (US 20180329644 A1) further in view Hu el. (US 20230244525 A1) further in view of Gupta et al. (US 20170036344 A1).
Regarding claim 6 Gupta expressly discloses wherein at least one processing unit of the first or the second processing units comprises at least one instruction primitive circuit (see Gupta paragraph [0054], the control path can be processed to produce a set of mid-level to high-level control instructions. These higher-level control instructions can be decomposed into a set of control primitives, which are preferably sent to the robot and can additionally be exposed through the user interface. Control primitives can include instructions like left (10), right (10), forward (2.3), sound (recording1. mp3), and right arm (10, 5). Decomposing a control path into control primitives can illustrate how a user could programmatically construct a control path).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Gupta into the method of Groen to have at least one instruction primitive circuit. Here, combining Gupta with Groen, which are both related to data processing improves Groen by providing improvement system to create a new and useful system and method for reinforcing programming education through robotic feedback (see Gupta paragraph [0003]).
Regarding claim 7 Gupta expressly wherein the at least one processing unit comprises a plurality of instruction primitive circuits operable to combine to perform at least one higher-level instruction (see Gupta paragraph [0054], the control path can be processed to produce a set of mid-level to high-level control instructions. These higher-level control instructions can be decomposed into a set of control primitives, which are preferably sent to the robot and can additionally be exposed through the user interface. Control primitives can include instructions like left (10), right (10), forward (2.3), sound (recording1. mp3), and right arm (10, 5). Decomposing a control path into control primitives can illustrate how a user could programmatically construct a control path).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Gupta into the method of Groen to have at least one instruction primitive circuit. Here, combining Gupta with Groen, which are both related to data processing improves Groen by providing improvement system to create a new and useful system and method for reinforcing programming education through robotic feedback (see Gupta paragraph [0003]).
Claim 10 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Groen et al. (US 7885320 B1) in view of Das et al. (US 20180329644 A1) further in view Hu el. (US 20230244525 A1) further in view of Prieditis et al. (US 10454496 B1).
Regarding claim 10, Prieditis expressly discloses, wherein at least one transform comprises tiling data for n-dimensional tiled processing (see Prieditis col. 2, lines 62-67, facilitate compression of multiple patches, tessellated (tiled) across the data, where a patch comprises an n-dimensional piece of data comprising multiple channels. Multiple such patches can be compressed and downloaded such that an entire piece of data (e.g., a database, an image, or a video) can be decompressed on the receiver's side).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Prieditis into the method of Groen to have tiling data for n-dimensional tiled processing. Here, combining Prieditis with Groen, which are both related to data processing improves Groen by providing system that can leverage the particulars of the data being compressed while adapting to the bandwidth at hand (see Prieditis col. 2, lines 1-3).
Claims 13 and 18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Groen et al. (US 7885320 B1) in view of Das et al. (US 20180329644 A1) further in view Hu el. (US 20230244525 A1) further in view of Beckman (US 20200162584).
Regarding claims 13 and 18, Beckman discloses wherein transmitting the first and second relative output data comprises providing the first and second relative output data by a direct data-passing interface to a compression/decompression engine (see Beckman, paragraph [0013], an indication of whether the at least one forward match and the at least one backward match occur for the current byte string for use in compressing the input data stream based on the matches).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Beckman into the method of Groen to have a direct data-passing interface to a compression/decompression engine. Here, combining Beckman with Groen, which are both related to data processing improves Groen by providing system for effienctly performing packet stream processing of high-capacity network and storage workloads of modern network (see Beckman paragraph [0003]).
Claims 14 and 19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Groen et al. (US 7885320 B1) in view of Das et al. (US 20180329644 A1) further in view Hu el. (US 20230244525 A1) further in view of Raupp Da Rosa (US 20170262389 A1).
Regarding claims 14 and 19, Raupp Da Rosa expressly discloses, wherein transmitting the first and second relative output data comprises providing the first and second relative output data by a direct data-passing interface to a direct memory access controller (see Raupp Da Rosa paragraph [0058], during a data exchange, at least one of said transmitting and receiving computation nodes calling upon an additional transmitting or receiving device of its direct memory access controller in order to exchange data between outside said computation node via the network and the work area of its processor, without passing through its sharing area).
It would have been obvious to a person of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of Raupp Da Rosa into the method of Groen to have a direct memory access controller. Here, combining Raupp Da Rosa with Groen, which are both related to data processing improves Groen by providing mechanisms and protocols making it possible to optimize the functioning of data exchanges (see Raupp Da Rosa paragraph [0002]).
Remarks
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sghiouer (US 20210200749 A1) discloses receiving a plurality of data input streams from different data providers, the computing device comprising a data processing unit and comprising a group of interconnected processing modules through which the first plurality of data streams pass to prepare the output dataset, the plurality of data input streams and the output dataset being different.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DINKU W GEBRESENBET whose telephone number is (571)270-1636. The examiner can normally be reached between 8:00AM-5:00PM.
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/DINKU W GEBRESENBET/Primary Examiner, Art Unit 2164