DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/19/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over McClain et al. (US 6,731,536) and further in view of Applicant’s Admitted Prior Art (APA herein after).
As per claim 12, McClain teaches 12. A system (McClain: abstract), comprising: [[a master device configured to]] select a boot block password (McClain: col. 6, lines 28-30: “the customer must first program the password”; abstract: “The memory also includes areas, whose protection state is controlled by an input signal, for storing boot code in a protected manner”; col. 7, lines 25-29; the customer programming the password inherently teaches customer selects the password and programs the password into the memory); and
a memory device [[coupled to the master device]], wherein the memory device comprises a [[NAND]] memory array (McClain: fig. 1 shows flash memory array) comprising a boot block (McClain: col. 7, lines 25-29: “typically the sectors containing boot code”), wherein the memory device is configured to receive the boot block password selected by the master device as part of a memory access of the memory device and program the boot block password into the memory device (McClain: col. 6, lines 28-30: “the customer must first program the password”; abstract: “The memory also includes areas, whose protection state is controlled by an input signal, for storing boot code in a protected manner”; taught as the customer programs the password, which means the selected password is sent with the access command e.g., write command or program password command and the memory device will program the customer selected password in the memory device).
McClain teaches a flash memory device (fig. 1); however, McClain expressly fails to teach NAND flash memory. McClain also teaches customer selecting the password, which requires a master device, however McClain expressly fails to teach a master device. APA teaches NAND flash memory device with master device transferring data and NAND flash memory including boot blocks storing boot codes (APA: pars. [0005] – [0007]). Thus, it would have been obvious to one having ordinary skill at the time of the invention to provide a NAND flash memory with boot code and master device with the boot block and securing boot block with password as taught by McClain to provide high storage density and high endurance memory with low cost of the storage device.
As per claim 13, McClain and APA teach wherein the master device is configured to select the boot block password as an n-bit password (McClain: col. 2, lines 63-67: 64-bit password).
As per claim 14, McClain and APA teach wherein the NAND memory array comprises a non-volatile area. McClain teaches flash memory and APA teaches NAND flash memory which inherently comprises a non-volatile area (McClain: claim 13).
As per claim 15, McClain and APA teach wherein the boot block password is programmed into the non-volatile area of the NAND memory array (McClain: claim 13).
As per claim 16, McClain and APA teach wherein the NAND memory array comprises a one-time programmable area (McClain: abstract, claim 13).
As per claim 17, McClain and APA teach wherein the boot block password is programmed into the one-time programmable area of the NAND memory array (McClain: abstract; claim 13).
Claim 18 is directed to the method and is similar in scope with claim 12 above. Thus, claim 18 is rejected under same rationales as applied to claim 12 above (McClain: claim 1 teaches method).
Claims 19 and 20 are similar in scope with claims 15 and 17 above and thus rejected under same rationales as applied to claims 15 and 17 above.
Claims 1-4 and 6-11 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Clark (US 5,448,045) and further in view of Ishida (US 2006/0242425) and McClain et al. (US 6,731,536).
As per claim 1, Clark teaches a system, comprising: a master device (Clark: fig. 1, item 10); and a memory device coupled to the master device (Clark: fig. 1, item 22: smart card), wherein the memory device comprises: a memory array; and [[a register, wherein the register is configured]] receive a password transmitted from the master device and [[store the password received from the master device as a received password]], wherein read access to at least a portion of the memory array is enabled if the received password is validated via comparison of the received password with a stored value (Clark: fig. 6; col. 5, lines 35-47: “The authorization information may be a password entered by a user and verified by the device (by comparison with a pre-stored password for the user); or biometric information (e.g. a fingerprint) about a user. The device may be a pocket-sized card containing the microprocessor and the memory (e.g., a smartcard). The critical information may include boot-sector information”; col. 11, lines 20-44; taught as the smartcard is waiting for the password and when the smartcard gets password from the computer system it validates the password and allows reding of data in its memory including boot code). Clark expressly fails to teach a register configured to receive password from the master device. However, Clark teaches the smartcard is receiving password and validating the password inherently requires some type of memory for storing received password and comparing with already stored password for validation).
Ishida fig. 1, shows the memory device including password memory circuit storing the verifying password previously stored (par. [0018]) and password input register for receiving the password provided by the master device and compared with the password stored in the password memory circuit (par. [0054]). Thus, it would have been obvious to one having ordinary skill in the art at the time of the invention to provide registers for storing and comparing the passwords provided by the master device.
Clark (col. 12, lines 29-46) teaches that boot sector is read protected and write protected by the passwords, which prevents users from inadvertently or deliberately corrupting critical data on the smartcard. However, Clark and Ishida fail to teach a second register, wherein the second register when in operation stores an indication of whether to enable or prevent a write access or an erase access to the portion of the memory array, wherein alteration of the indication is permitted only subsequent to validation of the received password via the comparison of the received password with the stored value.
McClain teaches a second register, wherein the second register when in operation stores an indication of whether to enable or prevent a write access or an erase access to the portion of the memory array, wherein alteration of the indication is permitted only subsequent to validation of the received password via the comparison of the received password with the stored value (McClain: col. 3, line 25 – col. 4, line 49; col. 6, lines 28-30: “the customer must first program the password”; abstract: “The memory also includes areas, whose protection state is controlled by an input signal, for storing boot code in a protected manner”; taught as the customer programs the password, which means the selected password is sent with the access command e.g., write command or program password command and the memory device will program the customer selected password in the memory device and once the write protection bit is set which prevents the contents of flash being changed; the DPB or PPB protection bits are the second register, which is when set prevents write access to the boot sector or any other sector without providing password). Thus, it would have been obvious to one having ordinary skill in the art at the time of the invention to provide a second register (protection bit with password protection) as taught by McClain to provide inadvertent or deliberately corrupting or overwriting the protected sectors of the memory device.
As per claim 2, Clark, Ishida and McClain teach wherein the at least a portion of the memory array comprises a boot block space of the memory array. Clark fig. 6, item 42 teaches boot sector; McClain: abstract teaches area/sector storing boot code.
As per claim 3, Clark, Ishida and McClain teach wherein the at least a portion of the memory array comprises a non-boot block space of the memory array (Clark: fig. 6, item 48; McClain: col. 2, lines 13-65).
As per claim 4, Clark, Ishida and McClain teach wherein the at least a portion of the memory array comprises an entirety of the memory array (McClain: col. 4, lines 20-50: protection state of each sector is determined means all sectors (entire memory array) can be protected or individual sectors can be protected).
As per claim 6, Clark, Ishida and McClain teach wherein the at least a portion of the memory array comprises a block region comprising one or more blocks of the memory array (McClain: col. 4, lines 20-50: protection state of each sector is determined means all sectors (entire memory array) can be protected or individual sectors or group of sectors can be protected).
As per claim 7, Clark, Ishida and McClain teach wherein the block region is user-definable or wherein the block region comprises an entire boot area. As explained with respect to claim 1 above, Clark and McClain teach boot sectors are read and/or write protected with password and lock bits.
As per claim 8, Clark, Ishida and McClain teach wherein the master device is configured to: initiate a read operation as the read access; initiate a write operation as the write access; and initiate an erase operation as the erase access. It is inherent that when the storage device/smartcard connected to the host, the host/master device initiate read, write or erase operations.
As per claim 9, Clark, Ishida and McClain teach wherein the memory device is configured to track a number of unsuccessful attempts in which the master device attempts to access the at least a portion of the memory array and prevent further accesses to the portion of the memory array when the number of unsuccessful attempts reaches a threshold value (Clark: col. 26-44: only a limited number of failed attempts allowed).
As per claim 10, Clark, Ishida and McClain teach wherein the memory device is configured to authenticate the master device responsive to comparing the received password with the stored value to validate the received password (Clark: col. 5, lines 34-46: “The authorization information may be a password entered by a user and verified by the device (by comparison with a pre-stored password for the user)”; McClain: col. 5, line 63 – col. 6, line 23).
As per claim 11, Clark, Ishida and McClain teach wherein the memory array is configured to store the stored value (McClain: claim 13; Clark: col. 6, lines 4-8).
Claim 5 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Clark (US 5,448,045), Ishida (US 2006/0242425) and McClain et al. (US 6,731,536) as applied to claim 1 above, and further in view of Xie (US 2006/0248267).
As per claim 5, Clark, Ishida and McClain fail to teach wherein the at least a portion of the memory array comprises an individual page within a particular block of the memory array. Xie teaches wherein the at least a portion of the memory array comprises an individual page within a particular block of the memory array (Xie: pars. [0005], [0025], [0026]). Thus, it would have been obvious to one having ordinary skill in the art at the time of the invention to provide protection to the subsectors (pages of the particular block) as taught by Xie to provide protection to individual portions of the pages of the blocks of memory device.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11,868,278. Although the claims at issue are not identical, they are not patentably distinct from each other because claims of current application are anticipated by the claims of the patent ‘278.
App. No. 19/243,471
U.S. Patent No. 11,868,278
1. A system, comprising: a master device; and a memory device coupled to the master device, wherein the memory device comprises: a memory array; and a register, wherein the register is configured receive a password transmitted from the master device and store the password received from the master device as a received password, wherein read access to at least a portion of the memory array is enabled if the received password is validated via comparison of the received password with a stored value; and a second register, wherein the second register when in operation stores an indication of whether to enable or prevent a write access or an erase access to the portion of the memory array, wherein alteration of the indication is permitted only subsequent to validation of the received password via the comparison of the received password with the stored value.
2. The system of claim 1, wherein the at least a portion of the memory array comprises a boot block space of the memory array.
3. The system of claim 1, wherein the at least a portion of the memory array comprises a non-boot block space of the memory array.
4. The system of claim 1, wherein the at least a portion of the memory array comprises an entirety of the memory array.
5. The system of claim 1, wherein the at least a portion of the memory array comprises an individual page within a particular block of the memory array.
6. The system of claim 1, wherein the at least a portion of the memory array comprises a block region comprising one or more blocks of the memory array.
7. The system of claim 6, wherein the block region is user-definable or wherein the block region comprises an entire boot area.
8. The system of claim 1, wherein the master device is configured to: initiate a read operation as the read access; initiate a write operation as the write access; and initiate an erase operation as the erase access.
9. The system of claim 1, wherein the memory device is configured to track a number of unsuccessful attempts in which the master device attempts to access the at least a portion of the memory array and prevent further accesses to the portion of the memory array when the number of unsuccessful attempts reaches a threshold value.
10. The system of claim 1, wherein the memory device is configured to authenticate the master device responsive to comparing the received password with the stored value to validate the received password.
11. The memory device of claim 1, wherein the memory array is configured to store the stored value.
1. A memory device, comprising: a memory array; a serial interface controller configured to interface with a master device; a register coupled to the serial interface controller, wherein the register is configured receive a password from the master device via the serial interface controller and store the password received from the master device as a received password, wherein read access to at least a portion of the memory array is enabled if the received password is validated via comparison of the received password with a stored value; and a second register coupled to the serial interface controller, wherein the second register when in operation stores an indication of whether to enable or prevent write or erase access to the portion of the memory array, wherein alteration of the indication is permitted only subsequent to validation of the received password via the comparison of the received password with the stored value.
2. The memory device of claim 1, wherein the at least a portion of the memory array comprises a boot block space of the memory array.
3. The memory device of claim 1, wherein the at least a portion of the memory array comprises a non-boot block space of the memory array.
4. The memory device of claim 1, wherein the at least a portion of the memory array comprises an entirety of the memory array.
5. The memory device of claim 1, wherein the at least a portion of the memory array comprises an individual page within a particular block of the memory array.
6. The memory device of claim 1, wherein the at least a portion of the memory array comprises a block region comprising one or more blocks of the memory array.
7. The memory device of claim 6, wherein the block region is user-definable.
8. The memory device of claim 6, wherein the block region comprises an entire boot area.
9. The memory device of claim 1, wherein the master device is configured to initiate a read operation as the access.
10. The memory device of claim 1, wherein the master device is configured to initiate a write operation as the access.
11. The memory device of claim 1, wherein the master device is configured to initiate an erase operation as the access.
12. The memory device of claim 1, wherein the serial interface controller is configured to initiate the access of the at least a portion of the memory array subsequent to receipt of a command when the received password is validated via comparison of the received password with the stored value.
14. The memory device of claim 1, wherein the memory device is configured to track a number of unsuccessful attempts in which the master device attempts to access the at least a portion of the memory array and prevent further accesses to the portion of the memory array when the number of unsuccessful attempts reaches a threshold value.
15. The memory device of claim 1, wherein the memory device is configured to authenticate the master device responsive to comparing the received password with the stored value to validate the received password.
16. The memory device of claim 1, wherein the memory array is configured to store the stored value.
Claims 12-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-19 of U.S. Patent No. 12,339,788. Although the claims at issue are not identical, they are not patentably distinct from each other because claims of current application are anticipated by claims of patent ‘788.
App. No. 19/243,471
U.S. Patent No. 12,339,788
12. A system, comprising: a master device configured to select a boot block password; and a memory device coupled to the master device, wherein the memory device comprises a NAND memory array comprising a boot block, wherein the memory device is configured to receive the boot block password selected by the master device as part of a memory access of the memory device and program the boot block password into the memory device.
13. The system of claim 12, wherein the master device is configured to select the boot block password as an n-bit password.
14. The system of claim 12, wherein the NAND memory array comprises a non-volatile area.
15. The system of claim 14, wherein the boot block password is programmed into the non-volatile area of the NAND memory array.
16. The system of claim 12, wherein the NAND memory array comprises a one-time programmable area.
17. The system of claim 16, wherein the boot block password is programmed into the one-time programmable area of the NAND memory array.
18. A method, comprising: selecting a boot block password for a NAND memory device; transmitting the boot block password to the NAND memory device; and programming the boot block password into the NAND memory device.
19. The method of claim 18, wherein programming the boot block password into the NAND memory device comprises storing the boot block password into a non-volatile area of a NAND memory array of the NAND memory device.
20. The method of claim 18, wherein programming the boot block password into the NAND memory device comprises storing the boot block password into a one-time programmable area of a NAND memory array of the NAND memory device.
9. A system, comprising: a master device configured to select a boot block password; and a memory device coupled to the master device, wherein the memory device comprises: a NAND memory array comprising a boot block; and a serial peripheral interface (SPI) controller coupled to the NAND memory array and the master device, wherein the SPI controller is configured to receive the boot block password selected by the master device as part of a memory access of the memory device and program the boot block password into the memory device.
10. The system of claim 9, wherein the master device is configured to select the boot block password as an n-bit password.
12. The system of claim 9, wherein the NAND memory array comprises a non-volatile area.
13. The system of claim 12, wherein the boot block password is programmed into the non-volatile area of the NAND memory array.
14. The system of claim 9, wherein the NAND memory array comprises a one-time programmable area.
15. The system of claim 14, wherein the boot block password is programmed into the one-time programmable area of the NAND memory array.
17. A method, comprising: selecting a boot block password for a NAND memory device; transmitting the boot block password to the NAND memory device via a serial peripheral interface (SPI) controller of the NAND memory device; and programming the boot block password into the NAND memory device.
18. The method of claim 17, wherein programming the boot block password into the NAND memory device comprises storing the boot block password into a non-volatile area of a NAND memory array of the NAND memory device.
19. The method of claim 17, wherein programming the boot block password into the NAND memory device comprises storing the boot block password into a one-time programmable area of a NAND memory array of the NAND memory device.
Conclusion
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAUSHIKKUMAR M PATEL whose telephone number is (571)272-5536. The examiner can normally be reached Mon-Fri: 9:00 AM - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim T Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Kaushikkumar M. Patel
Primary Examiner
Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138
Prosecution Insights