DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 6/19/2025.
Claims 1-22 are pending.
Claims 1-22 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 11-20, and 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Exemplary independent claim 1 recites “…write, at a first time, data to one or more memory cells of the memory system, the one or more memory cells associated with a first temperature at the first time; determine, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measure, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; and generate, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells” (independent claim 1, lines 5-21).
The Examiner is uncertain if the recitation of “determine, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time…” means any of the following possible interpretations:
“based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time,” “a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells” is determined at some point in time that occurs “between the first time at which the data was written to the one or more memory cells and the second time”;
“based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time,” “a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells” is determined as a difference between “a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells” that is associated with “a first temperature at the first time” and
“a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells” that is associated with “the second time”; or
some other possible, unconsidered interpretation.
The Examiner is uncertain if the recitation of “the read voltage calibration for the one or more memory cells” refers to “a read voltage calibration for the one or more memory cells at a second time that is after the first time” or to some other “read voltage calibration.”
The Examiner is uncertain if the recitation of “generate, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells” means any of the following possible interpretations:
“based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time,” “one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells” is generated;
“one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells” are generated using a combination of “the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…write, at a first time, data to one or more memory cells of the memory system, the one or more memory cells associated with a first temperature at the first time; determine, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measure, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; and generate, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells” to read “…write, at a first time, data to one or more memory cells of the memory system, the one or more memory cells of the memory system associated with a first temperature at the first time; determine a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells of the memory system between the first time at which the data was written to the one or more memory cells and a second time that is after the first time based at least in part on a read voltage calibration for the one or more memory cells of the memory system at the second time that is after the first time; measure, based at least in part on the read voltage calibration for the one or more memory cells of the memory system at the second time, a second temperature associated with the one or more memory cells of the memory system at a third time that is equal to or after the second time; and generate one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells based at least in part on both the shift in the read voltage associated with the first logic state of the plurality of logic states and a difference between the first temperature of the one or more memory cells of the memory system at the first time and the second temperature of the one or more memory cells of the memory system at the third time,”
Dependent claims 2-10, which ultimately depend from exemplary independent claim 1, are rejected for carrying the same deficiencies as exemplary independent claim 1.
The Examiner notes that independent claim 11 recites similar language in which the infinitives “[to] write,” “[to] determine,” “[to] measure,” “[to] generate” of exemplary independent claim 1 are replaced with “writing,” “determining,” “measuring,” and “generating.” Independent claim 11 is thus rejected for carrying the same deficiencies and interpreted similarly to exemplary independent claim 1, mutatis mutandis.
Dependent claims 12-20, which ultimately depend from independent claim 11, are rejected for carrying the same deficiencies as independent claim 11.
The Examiner notes that independent claim 21 recites similar language to exemplary independent claim 1, and is thus rejected for carrying the same deficiencies and interpreted similarly toe exemplary independent claim 1, mutatis mutandis.
Dependent claim 22, which ultimately depends from independent claim 21, is rejected for carrying the same deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by non-patent literature “Dynamic VTH Tracking for Cross-Temperature Suppression in 3D-TLC NAND Flash” (“Zambelli”).
As per claim 1, Zambelli substantially teaches a memory system (Zambelli, page 1, Fig. 1), comprising:
one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to: (Zambelli, page 1, Fig. 1; and page 3, column 1, paragraph beginning with “An alternative to the MRR method…”, where the system of Zambelli comprises a Triple Level Cell (TLC) NAND flash memory. The system of Zambelli may be embodied as a Solid State Drive (SSD) that comprises an SSD controller. Zambelli therefore substantially teaches one or more memory devices; and processing circuitry coupled with the one or more memory devices and configured to cause the memory system to);
write, at a first time, data to one or more memory cells of the memory system, the one or more memory cells associated with a first temperature at the first time: (Zambelli, page 1, column 1, section “Abstract,” where the 3D TLC NAND flash memory of Zambelli experiences a cross-temperature effect in which threshold voltage distributions are different when a second temperature at a second time of reading the 3D TLC NAND flash memory is different from a first temperature experienced at a first time when the 3D NAND flash memory was programmed (i.e., written). The Examiner notes that the 3D NAND flash memory was thus written at a first time while experiencing a first temperature. Zambelli therefore substantially teaches write, at a first time, data to one or more memory cells of the memory system, the one or more memory cells associated with a first temperature at the first time);
determine, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measure, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; and generate, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells: (Zambelli, page 2, column 1, section “III. CROSS-TEMPERATURE DYNAMIC VTH TRACKING (CTDVT) ALGORITHM”, to page 3, column 1, paragraph beginning with “The identification of the optimal…”, where the system of Zambelli determines a change (i.e., shift) in voltages to use for read operations that occur at a different temperature during a later time than was experienced during a programming operation at an original temperature during a first time. The change in voltage is either stored (e.g., in a look-up table) or calculated dynamically with each read operation that follows an earlier write operation in order to calculate a new voltage shift to use based on observed temperature differences between a temperature at a time of programming data and a temperature at a subsequent time of reading the programmed data. Zambelli therefore substantially teaches determine, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measure, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; and generate, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells).
As per claim 11, Zambelli substantially teaches a method by a memory system (Zambelli, page 1, Fig. 1), and section “Abstract”), comprising:
writing, at a first time, data to one or more memory cells of the memory system, the one or more memory cells associated with a first temperature at the first time: (Zambelli, page 1, column 1, section “Abstract,” where the 3D TLC NAND flash memory of Zambelli experiences a cross-temperature effect in which threshold voltage distributions are different when a second temperature at a second time of reading the 3D TLC NAND flash memory is different from a first temperature experienced at a first time when the 3D NAND flash memory was programmed (i.e., written). The Examiner notes that the 3D NAND flash memory was thus written at a first time while experiencing a first temperature. Zambelli therefore substantially teaches writing, at a first time, data to one or more memory cells of the memory system, the one or more memory cells associated with a first temperature at the first time);
determining, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measuring, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; generating, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells: (Zambelli, page 2, column 1, section “III. CROSS-TEMPERATURE DYNAMIC VTH TRACKING (CTDVT) ALGORITHM”, to page 3, column 1, paragraph beginning with “The identification of the optimal…”, where the system of Zambelli determines a change (i.e., shift) in voltages to use for read operations that occur at a different temperature during a later time than was experienced during a programming operation at an original temperature during a first time. The change in voltage is either stored (e.g., in a look-up table) or calculated dynamically with each read operation that follows an earlier write operation in order to calculate a new voltage shift to use based on observed temperature differences between a temperature at a time of programming data and a temperature at a subsequent time of reading the programmed data. Zambelli therefore substantially teaches determining, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measuring, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; generating, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells).
As per claim 21, Zambelli substantially teaches a non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to (Zambelli, page 1, Fig. 1, and section “Abstract”):
write, at a first time, data to one or more memory cells of a memory system, the one or more memory cells associated with a first temperature at the first time: (Zambelli, page 1, column 1, section “Abstract,” where the 3D TLC NAND flash memory of Zambelli experiences a cross-temperature effect in which threshold voltage distributions are different when a second temperature at a second time of reading the 3D TLC NAND flash memory is different from a first temperature experienced at a first time when the 3D NAND flash memory was programmed (i.e., written). The Examiner notes that the 3D NAND flash memory was thus written at a first time while experiencing a first temperature. Zambelli therefore substantially teaches write, at a first time, data to one or more memory cells of a memory system, the one or more memory cells associated with a first temperature at the first time);
determine, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measure, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; and generate, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells: (Zambelli, page 2, column 1, section “III. CROSS-TEMPERATURE DYNAMIC VTH TRACKING (CTDVT) ALGORITHM”, to page 3, column 1, paragraph beginning with “The identification of the optimal…”, where the system of Zambelli determines a change (i.e., shift) in voltages to use for read operations that occur at a different temperature during a later time than was experienced during a programming operation at an original temperature during a first time. The change in voltage is either stored (e.g., in a look-up table) or calculated dynamically with each read operation that follows an earlier write operation in order to calculate a new voltage shift to use based on observed temperature differences between a temperature at a time of programming data and a temperature at a subsequent time of reading the programmed data. Zambelli therefore substantially teaches determine, based at least in part on a read voltage calibration for the one or more memory cells at a second time that is after the first time, a shift in a read voltage associated with a first logic state of a plurality of logic states of the one or more memory cells between the first time at which the data was written to the one or more memory cells and the second time; measure, based at least in part on the read voltage calibration for the one or more memory cells, a second temperature associated with the one or more memory cells at a third time that is at the same as or after the second time; and generate, based at least in part on the shift in the read voltage associated with the first logic state and on a difference between the first temperature of the one or more memory cells at the first time and the second temperature of the one or more memory cells at the third time, one or more read voltage offset values associated with calibration of the plurality of logic states of the one or more memory cells).
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
USPGPUB 2023/0297471: teaches management of flash memory by detecting and characterizing errors based on a cross temperature.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
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