Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant detailed action is in response to Applicant's submission filed on 29 August 2025.
REJECTIONS NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See Contreras MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See Contreras MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See Contreras MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see Contreras 37 CFR 1.111(a). For a reply to final Office action, see Contreras 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See Contreras MPEP §§ 706.07(e) and 714.13.
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Claim 2-21 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-30 of U.S. Patent No. 12353725. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application are broader than and encompass the subject matter of the corresponding claims in the patent.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2,4-7,9-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated Contreras (US PG PUB No. 20220012187).
As per claim 2, a method, comprising:
obtaining telemetry data of one or more components of a memory device (see Contreras [0079]);
encrypting the telemetry data using a unique identifier of the memory device that corresponds to the one or more components of the memory device (see Contreras [0064]: “In other embodiments , the output of the hash algorithm can be signed or encrypted by the Elliptic Curve Digital Signature Algorithm ( EC - DSA ) or Rivest - Shamir - Adleman ( RSA )”);
storing, at the memory device and in an encrypted form, the telemetry data of the one or more components of the memory device (see Contreras [0064]); and
transmitting, to a host system as part of a procedure for verification of an identity of the one or more components of the memory device, first signaling that indicates the telemetry data, a change to the telemetry data relative to the stored telemetry data, or both (see Contreras [0085]).
As per claim 4, the method of claim 2, further comprising:
receiving, from the host system, a request for the telemetry data, wherein transmitting the first signaling is in response to the request (see Contreras [0084]).
As per claim 5, the method of claim 2, further comprising:
transmitting second signaling that indicates that the telemetry data is available at the memory device based on storing the telemetry data at the memory device, wherein transmitting the first signaling for the verification of the identity of the one or more components of the memory device is based on transmitting the second signaling (see Contreras [0081]).
As per claim 6, the method of claim 2, further comprising:
monitoring the one or more components of the memory device; and detecting the change to the telemetry data of the one or more components of the memory device relative to the stored telemetry data based on the monitoring, wherein transmitting the first signaling is based on detecting the change (see Contreras [0085]).
As per claim 7, the method of claim 6,
wherein the change to the telemetry data comprises a change to a temperature of the one or more components of the memory device, a change to a voltage of the one or more components of the memory device, a change to a speed of the one or more components of the memory device, a change to a capacitance of a channel between the one or more components of the memory device and the host system, a change to a memory array of the one or more components of the memory device, a flipped bit written to the one or more components of the memory device, an error associated with the one or more components of the memory device, or any combination thereof (see Contreras [0077]).
As per claim 9, the method of claim 2,
wherein the telemetry data of the memory device comprises a temperature of the memory device, a voltage of the memory device, a speed of the memory device, a capacitance of a channel that is between the memory device and the host system, a configuration of a memory array of the memory device, or any combination thereof (see Contreras FIG 6 and [0081]).
As per claim 10, the method of claim 2,
wherein transmitting the first signaling comprises transmitting the telemetry data in the encrypted form or an unencrypted form (see Contreras [0085]).
As per claim 11, the method of claim 2,
wherein the one or more components of the memory device comprise a dynamic random-access memory (DRAM) component of the memory device, and wherein the telemetry data corresponds to the DRAM component of the memory device (see Contreras [0080]).
As per claim 12, the method of claim 2, wherein storing the telemetry data
comprises:
storing the telemetry data to a set of addresses of the memory device, the set of addresses allocated for storage of data for the verification of the identity of the one or more components of the memory device (see Contreras FIG 6 and [0065]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3,8,13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Contreras (US PG PUB No. 20220012187) in view of Golov (US PG PUB No. 2020/0401533).
As per claim 3, the method of claim 2, further comprising:
However, Contreras does not expressly disclose but in the same field of endeavor Golov discloses
receiving, from the host system in response to the first signaling, second signaling that indicates one or more actions for performance by the memory device to verify the identity of the one or more components of the memory device (see Golov [0042])
It would have been obvious before the effective filing date of the invention to disable one or more features of the memory as taught by Golov.
The suggestion/motivation for doing so would have been for the benefit of preventing unauthorized access (see Golov [0004]).
Therefore it would have been obvious before the effective fling date of the invention to further enable or disable features of the DRAM for the benefit preventing unauthorized access to arrive at the invention as specified in the claims.
As per claim 8, the method of claim 2, further comprising:
However, Contreras does not expressly disclose but in the same field of endeavor Golov discloses
disabling, based on the procedure for the verification of the identity of the one or more components of the memory device indicating a modification to the memory device, one or more features of the memory device, wherein disabling the one or more features comprises flushing data from one or more memory cells of the memory device, locking access to the one or more memory cells, disabling performance of one or more commands, or any combination thereof (see Golov [0028])
It would have been obvious before the effective filing date of the invention to disable one or more features of the memory as taught by Golov.
The suggestion/motivation for doing so would have been for the benefit of preventing unauthorized access (see Golov [0004]).
Therefore it would have been obvious before the effective fling date of the invention to further enable or disable features of the DRAM for the benefit preventing unauthorized access to arrive at the invention as specified in the claims.
As per claim 13, a method, comprising:
receiving, at a host system as part of a procedure for verification of an identity of a memory device, first signaling that indicates telemetry data of one or more components of the memory device, wherein the telemetry data is encrypted with a unique identifier of the memory device (see Contreras FIG 6 and [0084]);
detecting, in accordance with the telemetry data of the one or more components of the memory device, a modification to the memory device (see Contreras [0085]); and
However, Contreras does not expressly disclose but in the same field of endeavor Golov discloses
transmitting, to the memory device, second signaling requesting the memory device to perform one or more actions in response to detecting the modification to the memory device (see Golov [0028])
It would have been obvious before the effective filing date of the invention to disable one or more features of the memory as taught by Golov.
The suggestion/motivation for doing so would have been for the benefit of preventing unauthorized access (see Golov [0004]).
Therefore it would have been obvious before the effective fling date of the invention to further enable or disable features of the DRAM for the benefit preventing unauthorized access to arrive at the invention as specified in the claims.
As per claim 14, the method of claim 13, further comprising:
receiving, as part of the procedure for verification of the identity of the one or more components of the memory device, third signaling that indicates that the telemetry data is available at the memory device (see Contreras [0084]); and
accessing a register of the memory device that stores the telemetry data, wherein accessing the register is in response to the third signaling, and wherein the first signaling is received in response to accessing the register (see Contreras [0081]).
As per claim 15, the method of claim 13, further comprising:
transmitting, to the memory device, a request for the telemetry data, wherein the first signaling is in response to the request (see Contreras [0084]).
As per claim 16, the method of claim 13,
wherein the modification to the memory device comprises a change to a temperature of the one or more components of the memory device, a change to a voltage of the one or more components of the memory device, a change to a speed of the one or more components of the memory device, a change to a capacitance of a channel between the one or more components of the memory device and the host system, a change to a memory array of the one or more components of the memory device, a flipped bit written to the one or more components of the memory device, an error associated with the one or more components of the memory device, or any combination thereof (see Contreras [0077]).
As per claim 17, the method of claim 13,
wherein the one or more actions comprise flushing data from one or more memory cells of the memory device, locking access to the one or more memory cells, disabling performance of one or more commands, or any combination thereof (see Golov [0042]).
As per claim 18, the method of claim 13,
wherein the one or more components of the memory device comprise a dynamic random-access memory (DRAM) component of the memory device, and wherein the telemetry data corresponds to the DRAM component of the memory device (see Contreras [0080]).
As per claim 19, the method of claim 13,
wherein the first signaling indicates the telemetry data, a change to the telemetry data, or both, and wherein the telemetry data of the memory device comprises a temperature of the memory device, a voltage of the memory device, a speed of the memory device, a capacitance of a channel that is between the memory device and the host system, a configuration of a memory array of the memory device, or any combination thereof (see Contreras FIG 6 and [0081]).
As per claim 20, the method of claim 13,
wherein detecting the modification to the memory device comprises detecting an addition of an interposer coupled with the memory device, an addition of cabling to the memory device, an addition of a socket to the memory device, a removal of a component from the memory device, or any combination thereof (see Contreras [0018]).
Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Contreras (US PG PUB No. 20220012187) in view of Kochar (US PG PUB No. 2015/0301754).
As per claim 21, an apparatus (see Contreras FIG 2: 200), comprising:
one or more components removable from the apparatus (See FIG 2: 100), the one or more components comprising:
an array of memory cells that each comprise capacitive storage elements (see FIG 2: 260); and
one or more [fuse] elements configured to store a unique identifier corresponding to the one or more components (See FIG 1: 122); and
a transceiver configured to:
obtain telemetry data of the one or more components of the apparatus device (see Contreras [0079]);
encrypt the telemetry data using the unique identifier of the memory device that corresponds to the one or more components of the apparatus (see Contreras [0064]: “In other embodiments , the output of the hash algorithm can be signed or encrypted by the Elliptic Curve Digital Signature Algorithm ( EC - DSA ) or Rivest - Shamir - Adleman ( RSA )”);
store, at the apparatus and in an encrypted form, the telemetry data of the one or more components of the apparatus (see Contreras [0064]); and
transmit, to a host system as part of a procedure for verification of an identity of the one or more components of the apparatus, first signaling that indicates the telemetry data, a change to the telemetry data relative to the stored telemetry data, or both (see Contreras [0085]).
However, Contreras does not expressly disclose but in the same field of endeavor Kochar discloses storing parameters in one or more fuse elements (see Kochar [0026]).
It would have been obvious before the effective filing date of the invetnio to modify Contreras to permanently store memory operation parameters as taught by Kochar.
The suggestion/motivation for doing so would have been for the benefit of preventing modification after the fact that may lead to unintended operation (see Kochar [0025]).
Therefore it would have been obvious to modify Contreras to implement a one time programmable fuse as taught by Kochar to guarantee against unintended operation to arrive at the invention as specified in the claims.
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 8544093 : A malicious-module identification device identifies and deactivates a malicious module operating in an information processing device connected thereto via a network. The malicious-module identification device is provided with a reception unit for receiving results of tampering detection from a plurality of modules for detecting tampering, and a determination unit for assuming that a module among the plurality of modules is a normal module, determining, based on the assumption, whether a contradiction occurs in the received results of tampering detection and identifying the module assumed to be a normal module as a malicious module when determining that a contradiction occurs. A deactivation unit outputs an instruction to deactivate the module identified as the malicious module (Abstract).
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KALPIT PARIKH whose telephone number is (571)270-1173. The examiner can normally be reached MON THROUGH FRI 9:30 TO 6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KALPIT PARIKH/
Primary Examiner, Art Unit 2137
KALPIT . PARIKH
Primary Examiner
Art Unit 2137
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