DETAILED ACTION
This office action is in response to the filed application 19/243,654 on June 19, 2025.
Claims 1-25 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on November 20, 2025 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-19, 21-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2023/0086696).
In regard to claim 1, Chen et al. teach a memory system, comprising:
one or more memory devices (memory, fig. 1); and
processing circuitry coupled with the one or more memory devices (host system, fig. 1) and configured to cause the memory system to:
read data (host initiate a memory access operation, a read operation, para. 13) from a page stripe of the memory system (a page stripe is a set of pages having the same page identifier, para. 12), the data stored in a first set of data transfer units within the page stripe and a second set of data transfer units within the page stripe that is different than the first set of data transfer units, the first set of data transfer units storing a first subset of the data that is associated with one or more errors (access host data and encoded error correction code, para. 12);
store, based at least in part on the first set of data transfer units including at least two data transfer units associated with the one or more errors, a reference value associated with recovery of the first subset of the data within the page stripe, wherein the reference value is based at least in part on a second subset of the data that is stored in the second set of data transfer units (host data can be encoded using error correcting code ECC to correct data errors that can occur during transmission or storage, the redundancy metadata (e.g., parity data such as one or more parity bits) to form a codeword, para. 13);
correct, based at least in part on the stored reference value and first recovery data associated with the first set of data transfer units, a first error of the one or more errors (first tier parity can be used for correcting errors due to relatively small granularity failures, para. 14); and
correct, based at least in part on the stored reference value and second recovery data associated with the first set of data transfer units, a second error of the one or more errors (second tier parity can be used for correcting larger granularity failures, para. 14).
In regard to claim 2, Chen et al. teach the memory system of claim 1, wherein, to read the data from the page stripe, the processing circuitry is further configured to cause the memory system to: read the data (read operation … access data at one or more memory pages of a plane of a memory device, para. 16) from a plurality of planes of the page stripe across a plurality of memory dies of the memory system, wherein each memory die comprises at least one plane associated with a first plane index (a block stripe is a collection of blocks, at least one from each plane of a die stripe, para. 12), the first set of data transfer units and the second set of data transfer units within one or more planes on one or more memory dies of the page stripe that are associated with the first plane index (host data and encoded error correction code, para. 12), and wherein the stored reference value is associated with the first plane index (provide redundancy for the data stored using one or more codewords, para. 17).
In regard to claim 3, Chen et al. teach the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: store, in at least one data transfer unit of a plane that is associated with the first plane index (distinct portions, planes, of the memory devices can be specified to store specific type of redundancy metadata, para. 20) and is included in a final memory die of the plurality of memory dies, information that indicates a first combination of the first subset of the data and the second subset of the data, wherein the reference value is based at least in part on a second combination of the second subset of the data that is stored in the second set of data transfer units and the stored information (RAIN parity data can be stored on five of the memory pages where the LUN spanning across 6 planes (24 memory pages), para. 21).
In regard to claim 4, Chen et al. teach the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: identify that a memory die of the plurality of memory dies is associated with a die-level failure, wherein at least one data transfer unit of the first set of data transfer units storing the first subset of the data is within the memory die; and perform a recovery of the memory die based at least in part on the stored reference value and one or more second reference values associated with one or more second plane indexes, wherein performing the recovery of the memory die comprises recovering the first subset of the data based at least in part on the stored reference value and recovering second data within the memory die based at least in part on the one or more second reference values (large codewords can be protected in the event of memory device failure, para. 21).
In regard to claim 5, Chen et al. teach the memory system of claim 1, wherein, to read the data from the page stripe, the processing circuitry is further configured to cause the memory system to: read the data from the first set of data transfer units and the second set of data transfer units within a plurality of planes of the page stripe and across a plurality of memory dies of the memory system, wherein each memory die comprises one or more planes associated with one or more plane indexes, and wherein the stored reference value is associated with a page stripe index of the page stripe (RAIN redundancy metadata and LUN redundancy metadata can recover data items at LUNs of one or more memory devices of the memory sub-system after a memory access failure, para. 21).
In regard to claim 6, Chen et al. teach the memory system of claim 5, wherein the processing circuitry is further configured to cause the memory system to: store, in at least one data transfer unit of a final plane of the plurality of planes of the page stripe, information that indicates a first combination of the data stored across the first set of data transfer units and the second set of data transfer units, wherein the reference value is based at least in part on a second combination of the second subset of the data that is stored in the second set of data transfer units and the stored information (RAIN schemes where large codewords can be split between multiple planes, para. 18).
In regard to claim 8, Chen et al. teach the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: generate the reference value based at least in part on a combination of respective data from each data transfer unit of the second set of data transfer units in accordance with a logical operation, wherein storing the reference value is based at least in part on the generating (generate one or more RAIN standard codewords based on an XOR operation applied to the host data stored at a particular number of data locations of one or more logical units, LUNs (e.g., page, block) of the memory sub-system, para. 17).
In regard to claim 9, Chen et al. teach the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
generate the first recovery data for recovery of the first error within a first data transfer unit of the first set of data transfer units, wherein generating the first recovery data is based at least in part on a first combination of a first subset of the first set of data transfer units that is different than the first data transfer unit, and wherein correcting the first error is based at least in part on a second combination of the reference value with the first recovery data (first tier parity can be used for correcting errors due to relatively small granularity failures, para. 14); and
generate the second recovery data for recovery of the second error within a second data transfer unit of the first set of data transfer units, wherein generating the second recovery data is based at least in part on a third combination of a second subset of the first set of data transfer units that is different than the second data transfer unit, and wherein correcting the second error is based at least in part on a fourth combination of the reference value with the second recovery data (second tier parity can be used for correcting larger granularity failures, para. 14).
In regard to claim 10, Chen et al. teach the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: receive a command to read the data from the page stripe of the memory system, wherein reading the data is based at least in part on the command; and transmit the data responsive to the command based at least in part on correcting the first error and correcting the second error (determine memory access failure occurred on a section that stores RAIN parity data, para. 60, regenerates the RAIN parity and the LUN parity using the host data and additional parity data, para. 61).
In regard to claim 11, Chen et al. teach the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: perform an error correction operation based at least in part on reading the data from the page stripe of the memory system (each LUN can correspond to a stripe of memory pages across multiple plane, para. 45); and detect the one or more errors associated with the first subset of the data based at least in part on performing the error correction operation (recovering data using the redundancy metadata, para. 54-61, fig. 5).
In regard to claim 12, Chen et al. teach the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to: initiate a redundant array of independent not-and (RAIN) recovery operation based at least in part on reading the data from the page stripe of the memory system (RAIN standard codewords based on XOR operation, para. 17), wherein storing the reference value is based at least in part on a failure associated with the RAIN recovery operation, and wherein correcting the first error and the second error is in accordance with a turbo RAIN recovery operation different from the RAIN recovery operation (RAIN protection of large codewords, where large codewords can be split between multiple planes, para. 18-19).
In regard to claim 13, Chen et al. teach the memory system of claim 1, wherein the one or more errors comprise a plurality of uncorrectable errors (if host data fails and the corresponding data is lost or corrupted, the memory sub-system controller can reconstruct the lost/corrupt data based on an XOR operation among the rest of the host data and the redundancy metadata, para. 18).
In regard to claim 14, Chen et al. teach a method by a memory system, comprising:
reading data (host initiate a memory access operation, a read operation, para. 13) from a page stripe of the memory system (a page stripe is a set of pages having the same page identifier, para. 12), the data stored in a first set of data transfer units within the page stripe and a second set of data transfer units within the page stripe that is different than the first set of data transfer units, the first set of data transfer units storing a first subset of the data that is associated with one or more errors (access host data and encoded error correction code, para. 12);
storing, based at least in part on the first set of data transfer units including at least two data transfer units associated with the one or more errors, a reference value associated with recovery of the first subset of the data within the page stripe, wherein the reference value is based at least in part on a second subset of the data that is stored in the second set of data transfer units (host data can be encoded using error correcting code ECC to correct data errors that can occur during transmission or storage, the redundancy metadata (e.g., parity data such as one or more parity bits) to form a codeword, para. 13);
correcting, based at least in part on the stored reference value and first recovery data associated with the first set of data transfer units, a first error of the one or more errors (first tier parity can be used for correcting errors due to relatively small granularity failures, para. 14); and
correcting, based at least in part on the stored reference value and second recovery data associated with the first set of data transfer units, a second error of the one or more errors (second tier parity can be used for correcting larger granularity failures, para. 14).
In regard to claim 15, Chen et al. teach the method of claim 14, wherein reading the data from the page stripe comprises: reading the data (read operation … access data at one or more memory pages of a plane of a memory device, para. 16) from a plurality of planes of the page stripe across a plurality of memory dies of the memory system, wherein each memory die comprises at least one plane associated with a first plane index (a block stripe is a collection of blocks, at least one from each plane of a die stripe, para. 12), the first set of data transfer units and the second set of data transfer units within one or more planes on one or more memory dies of the page stripe that are associated with the first plane index (host data and encoded error correction code, para. 12), and wherein the stored reference value is associated with the first plane index (provide redundancy for the data stored using one or more codewords, para. 17).
In regard to claim 16, Chen et al. teach the method of claim 15, further comprising: storing, in at least one data transfer unit of a plane that is associated with the first plane index (distinct portions, planes, of the memory devices can be specified to store specific type of redundancy metadata, para. 20) and is included in a final memory die of the plurality of memory dies, information that indicates a first combination of the first subset of the data and the second subset of the data, wherein the reference value is based at least in part on a second combination of the second subset of the data that is stored in the second set of data transfer units and the stored information (RAIN parity data can be stored on five of the memory pages where the LUN spanning across 6 planes (24 memory pages), para. 21).
In regard to claim 17, Chen et al. teach the method of claim 15, further comprising: identifying that a memory die of the plurality of memory dies is associated with a die-level failure, wherein at least one data transfer unit of the first set of data transfer units storing the first subset of the data is within the memory die; and performing a recovery of the memory die based at least in part on the stored reference value and one or more second reference values associated with one or more second plane indexes, wherein performing the recovery of the memory die comprises recovering the first subset of the data based at least in part on the stored reference value and recovering second data within the memory die based at least in part on the one or more second reference values (large codewords can be protected in the event of memory device failure, para. 21).
In regard to claim 18, Chen et al. teach the method of claim 14, wherein reading the data from the page stripe comprises: reading the data from the first set of data transfer units and the second set of data transfer units within a plurality of planes of the page stripe and across a plurality of memory dies of the memory system, wherein each memory die comprises one or more planes associated with one or more plane indexes, and wherein the stored reference value is associated with a page stripe index of the page stripe (RAIN redundancy metadata and LUN redundancy metadata can recover data items at LUNs of one or more memory devices of the memory sub-system after a memory access failure, para. 21).
In regard to claim 19, Chen et al. teach the method of claim 18, further comprising: storing, in at least one data transfer unit of a final plane of the plurality of planes of the page stripe, information that indicates a first combination of the data stored across the first set of data transfer units and the second set of data transfer units, wherein the reference value is based at least in part on a second combination of the second subset of the data that is stored in the second set of data transfer units and the stored information (RAIN schemes where large codewords can be split between multiple planes, para. 18).
In regard to claim 21, Chen et al. teach the method of claim 14, further comprising: generating the reference value based at least in part on a combination of respective data from each data transfer unit of the second set of data transfer units in accordance with a logical operation, wherein storing the reference value is based at least in part on the generating (generate one or more RAIN standard codewords based on an XOR operation applied to the host data stored at a particular number of data locations of one or more logical units, LUNs (e.g., page, block) of the memory sub-system, para. 17).
In regard to claim 22, Chen et al. teach the method of claim 14, further comprising:
generating the first recovery data for recovery of the first error within a first data transfer unit of the first set of data transfer units, wherein generating the first recovery data is based at least in part on a first combination of a first subset of the first set of data transfer units that is different than the first data transfer unit, and wherein correcting the first error is based at least in part on a second combination of the reference value with the first recovery data (first tier parity can be used for correcting errors due to relatively small granularity failures, para. 14); and
generating the second recovery data for recovery of the second error within a second data transfer unit of the first set of data transfer units, wherein generating the second recovery data is based at least in part on a third combination of a second subset of the first set of data transfer units that is different than the second data transfer unit, and wherein correcting the second error is based at least in part on a fourth combination of the reference value with the second recovery data (second tier parity can be used for correcting larger granularity failures, para. 14).
In regard to claim 23, Chen et al. teach the method of claim 14, further comprising: receiving a command to read the data from the page stripe of the memory system, wherein reading the data is based at least in part on the command; and transmitting the data responsive to the command based at least in part on correcting the first error and correcting the second error (determine memory access failure occurred on a section that stores RAIN parity data, para. 60, regenerates the RAIN parity and the LUN parity using the host data and additional parity data, para. 61).
In regard to claim 24, Chen et al. teach a non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
read data (host initiate a memory access operation, a read operation, para. 13) from a page stripe of a memory system (a page stripe is a set of pages having the same page identifier, para. 12), the data stored in a first set of data transfer units within the page stripe and a second set of data transfer units within the page stripe that is different than the first set of data transfer units, the first set of data transfer units storing a first subset of the data that is associated with one or more errors (access host data and encoded error correction code, para. 12);
store, based at least in part on the first set of data transfer units including at least two data transfer units associated with the one or more errors, a reference value associated with recovery of the first subset of the data within the page stripe, wherein the reference value is based at least in part on a second subset of the data that is stored in the second set of data transfer units (host data can be encoded using error correcting code ECC to correct data errors that can occur during transmission or storage, the redundancy metadata (e.g., parity data such as one or more parity bits) to form a codeword, para. 13);
correct, based at least in part on the stored reference value and first recovery data associated with the first set of data transfer units, a first error of the one or more errors (first tier parity can be used for correcting errors due to relatively small granularity failures, para. 14); and
correct, based at least in part on the stored reference value and second recovery data associated with the first set of data transfer units, a second error of the one or more errors (second tier parity can be used for correcting larger granularity failures, para. 14).
In regard to claim 25, Chen et al. teach the non-transitory computer-readable medium of claim 24, wherein, to read the data from the page stripe, the instructions are executable by the one or more processors to: read the data (read operation … access data at one or more memory pages of a plane of a memory device, para. 16) from a plurality of planes of the page stripe across a plurality of memory dies of the memory system, wherein each memory die comprises at least one plane associated with a first plane index (a block stripe is a collection of blocks, at least one from each plane of a die stripe, para. 12), the first set of data transfer units and the second set of data transfer units within one or more planes on one or more memory dies of the page stripe that are associated with the first plane index (host data and encoded error correction code, para. 12), and wherein the stored reference value is associated with the first plane index (provide redundancy for the data stored using one or more codewords, para. 17).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0086696) in further view of Huang et al. (US 2021/0064495).
In regard to claim 7, Chen et al. does not explicitly teach the memory system of claim 1, wherein, to store the reference value, the processing circuitry is further configured to cause the memory system to: store the reference value for a duration, wherein the first error and the second error are corrected before an expiration of the duration; and overwrite, based at least in part on the duration expiring, the reference value with a second reference value associated with recovery of second data stored in a third set of data transfer units.
Huang et al. teach of an internal timer that checks if an operating condition related to the life remaining of the memory cells meets a boundary condition. Alter parameters of the RAIN protection to adjust the performance (para. 49-50, fig. 4).
It would have been obvious to modify the Chen et al. of a by adding b. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in providing a checks for operating condition and life remaining in the memory cells (para. 49).
In regard to claim 20, Chen et al. does not explicitly teach the method of claim 14, wherein storing the reference value comprises: storing the reference value for a duration, wherein the first error and the second error are corrected before an expiration of the duration; and overwriting, based at least in part on the duration expiring, the reference value with a second reference value associated with recovery of second data stored in a third set of data transfer units.
Huang et al. teach of an internal timer that checks if an operating condition related to the life remaining of the memory cells meets a boundary condition. Alter parameters of the RAIN protection to adjust the performance (para. 49-50, fig. 4).
Refer to claim 7 for motivational statement.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Nguyen et al. (US 2025/0226045) Micron, dynamic error correction
Li et al. (US 12,346,574) Micron, fault tolerant stripe refer to collection of management units
Storer (US 2014/0164694) RAIN configuration
Amoto et al. (US 10,176,039) RAIN mechanism for parity data restoration
Cadloni et al. (US 10,770,168) Micron, automatically schedule execution and adjust routine
Subbarao et al. (US 2020/0402605) two layer code with low parity cost
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Loan Truong whose telephone number is 408-918-7552. The examiner can normally be reached on 10AM-6PM PST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Ashish Thomas can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Loan L.T. Truong/Primary Examiner, Art Unit 2114 HYPERLINK "mailto:Loan.truong@uspto.gov" Loan.truong@uspto.gov
Prosecution Insights