NON-FINAL ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 12-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hinck (US 20230393740).
Regarding claim 1, Hinck teaches a memory system comprising: a plurality of memory chips mounted to a circuit board, wherein: the plurality of memory chips are configured to store error correction code (ECC) bits for corresponding data; and at least one memory chip of the plurality of memory chips is accessible via both a first memory subchannel and a second memory subchannel; (“Turning now to FIG. 2C, like in the examples of FIGS. 2A and 2B, each memory channel includes 4 pseudo channels or sub channels. The memory module 201C includes one rank of five 4-way pseudo split DRAM devices 220-1-220-5. The DRAM devices 220-1-220-5 of the memory module 201C include four data DRAM devices 220-1-220-4 and one ECC DRAM device 220-5. Each of the DRAM devices 220-1-220-5 include 4 slices.” ¶32). and a plurality of buffers mounted to the circuit board wherein at least one buffer of the plurality of buffers is configured to route signals for accessing the ECC bits and the corresponding data to the at least one memory chip via both the first memory subchannel and the second memory subchannel (“In one example, each slice transmits or receives data over a burst. Consider an example in which each slice outputs (or inputs) a burst for 32 cycles. If each slice has 2 I/Os (e.g., 2 data lanes, shown with a x2) then each slice output 64 bits. Therefore, in this example, 8 devices×64bits=512 bits or 64 Bytes per burst. In one such example, the ECC devices 100-5 and 100-6 are each outputting 64-bits per burst, resulting in SDDC operation.” ¶29).
Regarding claim 2, Hinck teaches wherein the at least one memory chip includes four memory die, (“One pseudo channel (e.g., PCH0) corresponds to the four slices of the DRAM device 300-1, a second pseudo channel (e.g., PCH1) corresponds to the four slices of the DRAM device 300-2, a third pseudo channel (e.g., PCH2) corresponds to the four slices of the DRAM device 300-3, and a fourth pseudo channel (e.g., PCH3) corresponds to the four slices of the DRAM device 300-4”.¶35); and wherein a first pair of the four memory die are allocated to the first memory subchannel and a second pair of the four memory die are allocated to the second memory subchannel (“FIG. 4 is a high-capacity memory module (e.g., 40 devices per DIMM) that enables 2X the capacity (e.g., from 96 GB and 128 GB, or another capacity). In one such example, the high capacity DIMM does not interleave the 4 pseudo channels per device, but rather only 2 pseudo channels per device” ¶39).
Regarding claim 3, Hinck teaches an additional memory chip of the plurality of memory chips is accessible exclusively via the first memory subchannel; and an additional buffer of the plurality of buffers is configured to route signals for accessing the ECC bits and the corresponding data to the additional memory chip via only the first memory subchannel (“For SDDC solutions today, a memory subsystem requires two ECC devices in addition to other N DRAM devices per subchannel within a memory configuration. These ECC devices provide an equal number of bits as written or read from a data device. For example, in DDR5 (Double Data Rate version 5), 8 data devices plus 2 ECC devices per sub-channel are needed to achieve SDDC.” ¶16).
Regarding claim 4, Hinck teaches The memory system of claim 3, wherein: a second additional memory chip of the plurality of memory chips is accessible exclusively via the second memory subchannel (“For example, FIG. 3 is a block diagram of an example of a memory module including 4-way pseudo split DRAM dies in which each pseudo channel corresponds to one die… a second pseudo channel (e.g., PCH1) corresponds to the four slices of the DRAM device 300-2” ¶35); and a second additional buffer of the plurality of buffers is configured to route signals for accessing the ECC bits and the corresponding data to the second additional memory chip via only the second memory subchannel (“These ECC devices provide an equal number of bits as written or read from a data device. For example, in DDR5 (Double Data Rate version 5), 8 data devices plus 2 ECC devices per sub-channel are needed to achieve SDDC. For other memory technologies, the total number of devices varies, but conventionally 2 additional devices are used to provide ECC” ¶16).
Regarding claim 5, Hinck teaches The memory system of claim 4, wherein: the additional memory chip comprises eight memory die allocated to the first memory subchannel; and the second additional memory chip comprises eight memory die allocated to the second memory subchannel (“The memory module 501 of FIG. 5 illustrates one rank with 20 4-way pseudo split DRAM devices. Each row of DRAM devices shown in FIG. 5 includes eight data DRAM devices” ¶40).
Regarding claim 6, Hinck teaches wherein each memory chip of the plurality of memory chips comprises dynamic random-access memory (DRAM). (“FIG. 1 is a block diagram of an example of a 4-way pseudo-split DRAM die” ¶4).
Regarding claim 7, Hinck teaches wherein the memory system comprises a dual in-line memory module (DIMM) (“FIG. 7A illustrates an example of a dual inline memory module (DIMM)” ¶8).
Regarding claim 8, Hinck teaches wherein the at least one buffer is configured to route at least one of command/address (CA) signals or data (DQ) signals to the at least one memory chip via both the first memory subchannel and the second memory subchannel (“the signal lines for CMD can be referred to as a “C/A bus” (or ADD/CMD bus, or some other designation indicating the transfer of commands (C or CMD) and address (A or ADD) information) and the signal lines for write and read DQ can be referred to as a “data bus.”” ¶56).
Regarding claim 9, Hinck teaches wherein each buffer of the plurality of buffers comprises a registered clock driver (RCD). (“t he memory module 501 includes an address repeater/clock repeater (e.g., a registered clock driver (RCD))” ¶4).
Regarding claim 12, Hinck teaches wherein the at least one buffer receives the signals via the first memory subchannel and the second memory subchannel (“The memory module 201C includes one rank of five 4-way pseudo split DRAM devices 220-1-220-5. The DRAM devices 220-1-220-5 of the memory module 201C include four data DRAM devices 220-1-220-4 and one ECC DRAM device 220-5.” ¶32).
Regarding claim 13, Hinck teaches A computing system, comprising: a processor; and a memory system communicatively coupled to the processor, the memory system configured to service memory access requests of the processor, wherein the memory system comprises:a plurality of memory chips mounted to a circuit board,wherein:the plurality of memory chips are configured to store error correction code (ECC) bits and corresponding data based on the memory access requests; (“Controller 850 includes command logic 852, which can decode command encoding received on command and address signal lines. Thus, command logic 852 can be or include a command decoder. With command logic 852, memory device can identify commands and generate internal operations to execute requested commands” ¶64); and at least one memory chip of the plurality of memory chips is accessible via both a first memory subchannel and a second memory subchannel; (“Turning now to FIG. 2C, like in the examples of FIGS. 2A and 2B, each memory channel includes 4 pseudo channels or sub channels. The memory module 201C includes one rank of five 4-way pseudo split DRAM devices 220-1-220-5. The DRAM devices 220-1-220-5 of the memory module 201C include four data DRAM devices 220-1-220-4 and one ECC DRAM device 220-5. Each of the DRAM devices 220-1-220-5 include 4 slices.” ¶32). and a plurality of buffers mounted to the circuit board, wherein at least one buffer of the plurality of buffers is configured to route signals for accessing the ECC bits and the corresponding data to the at least one memory chip via both the first memory subchannel and the second memory subchannel (“
Regarding claim 14, Hinck teaches wherein the processor is a central processing unit (CPU) or an accelerated unit (“Each separate processor can include a single processing unit, a multicore processing unit, or a combination. The processing unit can be a primary processor such as a CPU (central processing unit)” ¶50).
Regarding claim 15, Hinck teaches further comprising at least one additional memory system communicatively coupled to the processor, wherein the at least one additional memory system is configured to service additional memory access requests of the processor without handling ECC for the additional memory access requests (“Memory accesses may also be initiated by devices such as a network controller or hard disk controller. Such devices can be integrated with the processor in some systems or attached to the processer via a bus (e.g., PCI express), or a combination. System 800 can be implemented as an SOC (system on a chip) or be implemented with standalone components.” ¶50).
Regarding claim 16, Hinck teaches A method comprising: receiving a memory access request for a memory system (“Thus, command logic 852 can be or include a command decoder. With command logic 852, memory device can identify commands and generate internal operations to execute requested commands” ¶64);, the memory system comprising a plurality of memory chips mounted to a circuit board and at least one memory chip of the plurality of memory chips is accessible via both a first memory subchannel and a second memory subchannel; (Turning now to FIG. 2C, like in the examples of FIGS. 2A and 2B, each memory channel includes 4 pseudo channels or sub channels. The memory module 201C includes one rank of five 4-way pseudo split DRAM devices 220-1-220-5. The DRAM devices 220-1-220-5 of the memory module 201C include four data DRAM devices 220-1-220-4 and one ECC DRAM device 220-5. Each of the DRAM devices 220-1-220-5 include 4 slices” ¶32); routing, by at least one buffer of a plurality of buffers mounted to the circuit board, signals for accessing error correction code (ECC) bits and corresponding data of the memory access request to the at least one memory chip via both the first memory subchannel and the second memory subchannel; and storing the ECC bits and the corresponding data in the at least one memory chip based on the routed signals (““In one example, each slice transmits or receives data over a burst. Consider an example in which each slice outputs (or inputs) a burst for 32 cycles. If each slice has 2 I/Os (e.g., 2 data lanes, shown with a x2) then each slice output 64 bits. Therefore, in this example, 8 devices×64bits=512 bits or 64 Bytes per burst. In one such example, the ECC devices 100-5 and 100-6 are each outputting 64-bits per burst, resulting in SDDC operation.” ¶29).
Regarding claim 17, Hinck teaches wherein the at least one memory chip includes four memory die, and wherein routing the signals comprises: routing a first subset of the signals to a first pair of the four memory die via the first memory subchannel; and routing a second subset of the signals to a second pair of the four memory die via the second memory subchannel (“For example, FIG. 3 is a block diagram of an example of a memory module including 4-way pseudo split DRAM dies in which each pseudo channel corresponds to one die… a second pseudo channel (e.g., PCH1) corresponds to the four slices of the DRAM device 300-2” ¶35
Regarding claim 18, Hinck teaches further comprising routing, by an additional buffer of the plurality of buffers, signals for accessing the ECC bits and the corresponding data to an additional memory chip of the plurality of memory chips via only the first memory subchannel. (“For SDDC solutions today, a memory subsystem requires two ECC devices in addition to other N DRAM devices per subchannel within a memory configuration.” ¶16).
Regarding claim 19, Hinck teaches further comprising routing, by a second additional buffer of the plurality of buffers, signals for accessing the ECC bits and the corresponding data to a second additional memory chip of the plurality of memory chips via only the second memory subchannel (“For SDDC solutions today, a memory subsystem requires two ECC devices in addition to other N DRAM devices per subchannel within a memory configuration. These ECC devices provide an equal number of bits as written or read from a data device. For example, in DDR5 (Double Data Rate version 5), 8 data devices plus 2 ECC devices per sub-channel are needed to achieve SDDC.” ¶16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 11, and 20is/are rejected under 35 U.S.C. 103 as being unpatentable over Hinck in view of Hampel (US 20240012709).
Regarding claim 10, Hinck teaches the memory system of claim 1… wherein the backside memory connectors communicably connect the at least one buffer to pins of memory die of the at least one memory chip (“For example, the package 601 includes a substrate 603 over which two stacks 607A and 607B of pseudo split DRAM dies are disposed. Wired bonds 605 are shown, coupling the stacked DRAM devices. One stack 607A of DRAM devices includes four data DRAM devices, and a second stack 607B includes four data DRAM devices and two ECC DRAM devices. In one such example, a memory channel includes two such packages (e.g., two of the packages 601)” ¶43). Backside memory connector is interpreted as equivalent to the wire bonds which connect multiple dies of a single stacked memory chip. Hinck does not teach wherein the at least one buffer is configured to map input addresses of the signals to backside memory connectors of the first memory subchannel and the second memory subchannel.
Hampel teaches wherein the at least one buffer is configured to map input addresses of the signals to backside memory connectors of the first memory subchannel and the second memory subchannel (“For example, one or more of compute nodes 210a-210c may configure controller 231 with an error control scheme map 242 that associates memory physical address ranges used by subchannel memory controllers 237a-237b to identify error control schemes” ¶33). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the subchannel memory ECC methods of Hinck with the mapping of addresses to subchannels as described by Hampel. This would help identify what ECC scheme to select as stated in ¶33 and in the abstract (“The selection of the error control scheme may be made based on the fabric physical address and a lookup table or address range registers. The selection of the error control scheme may be made based on the memory device physical address and a lookup table or address range registers”).
Regarding claim 11, Hampel teaches wherein the at least one buffer receives the signals only via the first memory subchannel and routes the received signals via both the first memory subchannel and the second memory subchannel based on a mapping of input addresses to backside memory connectors (“Subchannel 1 ECC 235a is operatively coupled to MUX/DEMUX 227 and subchannel 1 memory controller 237a to produce, check, and communicate error control information for transactions directed to subchannel 1 memory controller 237a that use non-interleaved error control schemes. Subchannel 2 ECC 235b is operatively coupled to MUX/DEMUX 227 and subchannel 1 memory controller 237b. Subchannel 2 ECC 235b is operatively coupled to MUX/DEMUX 227 and subchannel 2 memory controller 237b to produce, check, and communicate error control information for transactions directed to subchannel 2 memory controller 237b that use non-interleaved error control schemes.” ¶34).
Regarding claim 20, Hampel teaches wherein routing the signals comprises: receiving the signals via only the first memory subchannel; and routing the received signals via both the first memory subchannel and the second memory subchannel to the at least one memory chip based on a mapping of input addresses to backside memory connectors (“Subchannel 1 ECC 235a is operatively coupled to MUX/DEMUX 227 and subchannel 1 memory controller 237a to produce, check, and communicate error control information for transactions directed to subchannel 1 memory controller 237a that use non-interleaved error control schemes. Subchannel 2 ECC 235b is operatively coupled to MUX/DEMUX 227 and subchannel 1 memory controller 237b. Subchannel 2 ECC 235b is operatively coupled to MUX/DEMUX 227 and subchannel 2 memory controller 237b to produce, check, and communicate error control information for transactions directed to subchannel 2 memory controller 237b that use non-interleaved error control schemes.” ¶34).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Keeth US20220121393 which describes the use of Chipkill/SDDC to correct errors within a subchannel.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN KEVIN MCNAMARA whose telephone number is (703)756-1884. The examiner can normally be reached Monday-Friday 7:30-5:00 EST.
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/SEAN KEVIN MCNAMARA/Examiner, Art Unit 2113
/PHILIP GUYTON/Primary Examiner, Art Unit 2113
Prosecution Insights