DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/20/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 12, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9, and 16, respectively, of U.S. Patent No. 11,960,885 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every claim limitation in the application under examination is recited in the conflicting reference patent claims. The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 11,960,885 B2
1. A method, for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network, comprising: compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for an execution of the complex computation;
configuring a set of programmable controllers on the heterogeneous set of
computational nodes with the set of instructions;
executing the set of instructions using the set of programmable controllers; and
routing the data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogeneous set of computational nodes; and (iii) in response to the execution of the set of instructions.
1. A method, for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network, comprising:
compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for an execution of the complex computation;
configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions;
executing the set of instructions using the set of programmable controllers; and
routing the data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogeneous set of computational nodes; and (iii) in response to the execution of the set of instructions; wherein: (i) the heterogeneous set of computational nodes includes a set of processing cores in at least two multicore processors; (ii) the network includes a network hierarchy with at least a core level and a chip level; (iii) each computational node in the heterogeneous set of computational nodes includes a router from a set of routers; (iv) the routing of the data through the network includes the set of routers transitioning the data through the core level and the chip level; (v) the network hierarchy includes a server level and a rack level; (vi) at least one of the links is an ethernet link; (vii) the routing of the data through the network includes the set of routers transiting the data through the server level and the rack level; and (viii) the ethernet link does not use an ethernet switch.
Claims 9 and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,960,885 B2.
Claims 1, 12, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, and 21, respectively, of U.S. Patent No. 12,367,041 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every claim limitation in the application under examination is recited in the conflicting reference patent claims. The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 12,367,041 B2
1. A method, for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network, comprising: compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for an execution of the complex computation;
configuring a set of programmable controllers on the heterogeneous set of
computational nodes with the set of instructions;
executing the set of instructions using the set of programmable controllers; and
routing the data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogeneous set of computational nodes; and (iii) in response to the execution of the set of instructions.
1. A method, for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network, comprising: compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for an execution of the complex computation, the set of instructions for routing data and a set of instructions for the execution of the complex computation being generated prior to the execution of the complex computation;
configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions for routing data;
executing the set of instructions for routing data using the set of programmable controllers; and
routing the data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogeneous set of computational nodes; and (iii) in response to the execution of the set of instructions for routing data.
Claims 2 and 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4, respectively, of U.S. Patent No. 12,367,041 B2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Halpern et al (hereinafter Halpern), US 20190303153 A1, in view of Thouppuarachchi et al (hereinafter Thouppuarachchi), US 20220229880 A1, in view of Zhang et al (hereinafter Zhang), US 20160315847 A1.
Referring to claim 1, Halpern discloses a method, for executing a complex computation on a heterogenous set of computational nodes linked together by a set of links in a network [figs. 1 and 6; paragraphs 136, 167, “Depicted accelerator tile 100 is a heterogeneous array comprised of several kinds of PEs coupled together via an interconnect network 104”; “the composition of light-weight processing elements (PE) connected by an inter-PE network”, see heterogeneous array of PEs linked together by set of links (fig. 6)].
Halpern does not explicitly disclose compiling, a set of instructions for routing data for an execution of the complex computation;
configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions;
executing the set of instructions using the set of programmable controllers; and
routing the data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogenous set of computational nodes; and (iii) in response to the execution of the set of instructions.
However, Thouppuarachchi discloses compiling, a set of instructions for routing data for an execution of the complex computation [paragraphs 88, 78, “The compiler generates 1112 an instruction stream configuration based upon the determined set of arithmetic operations and set of neighbor routing connections. The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving”; “The goal of the compiler is to, given a particular partial differential equation (or similar problem) that will be applied to all points on a 1, 2 or 3 dimensional grid, determine how to configure the computational array to compute the equation”];
configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions [paragraphs 82, 88, 94, 78, “The compiler generates 1112 an instruction stream configuration”; “In some embodiments, the compiler assigns a routing ID to all of the inputs/outputs and neighbor connections to each ALU”; “The goal of the compiler is to, given a particular partial differential equation (or similar problem) that will be applied to all points on a 1, 2 or 3 dimensional grid, determine how to configure the computational array to compute the equation”];
executing the set of instructions using the set of programmable controllers [paragraph 25, “Each point processor comprises a computational element (e.g., an ALU) and a storage element (e.g., a register file), and is configured to receive data corresponding to a respective node of a domain and generate a value for the node for a next time step, based upon instructions received over time via an instruction stream. In some embodiments, the array of point processors is divided into slices which receive data and instructions in a staggered manner. Because all the data and computational requirements of the point processors are determined at compile time, the point processors do not need to perform any dynamic scheduling, allowing for a greater proportion of on-chip area to be allocated towards useful computation”]; and
routing the data: (i) through the network [paragraphs 88, 50, 82, The compiler generates 1112 an instruction stream configuration…The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving; “the node data may be routed through successive point processors of the array to reach the particular point processor, where the routing is pre-scheduled by the compiler”; “In addition, the compiler performs routing between point processors of the computational array, in accordance with some embodiments”]; (ii) to facilitate the execution of the complex computation by the heterogenous set of computational nodes [figs. 2-3, problem package comprising the complex computation; also see fig. 10 where the compiler the compiler performs routing between point processors of the computational array to facilitate execution of the complex computation (see fig. 8 and graph on left side of fig. 10 showing complex computation)]; and (iii) in response to the execution of the set of instructions [paragraphs 88, 50, 82, The compiler generates 1112 an instruction stream configuration…The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving; “the node data may be routed through successive point processors of the array to reach the particular point processor, where the routing is pre-scheduled by the compiler”; “In addition, the compiler performs routing between point processors of the computational array, in accordance with some embodiments”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Thouppuarachchi in the method of Halpern, to implement compiling, a set of instructions for routing data for an execution of the complex computation; configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions; executing the set of instructions using the set of programmable controllers; and routing the data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogenous set of computational nodes; and (iii) in response to the execution of the set of instructions, in order allow for a greater proportion of on-chip area to be allocated towards useful computation [Thouppuarachchi, paragraph 25].
The modified Halpern does not explicitly disclose using a table of bandwidth values for the set of links in the network.
However, Zhang discloses using a table of bandwidth values for the set of links in the network [Abstract, “a network control node calculates a forwarding path from a source node to a destination node”; paragraph 10, “in a process of calculating a path result and configuring a flow table shown in FIG. 1, a method for calculating a path of an SDN mainly considers external constraint conditions such as link cost (such as the number of hops), a link bandwidth and a link attribute; and after calculating a forwarding path according to an existing path algorithm, an SDN controller transmits a flow table to each OFS on the forwarding path].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Zhang in the method of the modified Halpern, to implement using a table of bandwidth values for the set of links in the network, in order calculate an optimal network path from the source node and the destination node with the effect of improving path calculation correctness [Zhang, paragraph 73].
Referring to claim 12, Halpern discloses a method for executing a complex computation on a heterogenous set of computational nodes linked together by a set of links in a network [figs. 1 and 6; paragraphs 136, 167, “Depicted accelerator tile 100 is a heterogeneous array comprised of several kinds of PEs coupled together via an interconnect network 104”; “the composition of light-weight processing elements (PE) connected by an inter-PE network”, see heterogeneous array of PEs linked together by set of links (fig. 6)].
Halpern does not explicitly disclose compiling, using a machine model of the set of links, a set of instructions for routing data for an execution of the complex computation,
configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions;
executing the set of instructions using the set of programmable controllers; and
routing data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogenous set of computational nodes; and (iii) in response to the execution of the set of instructions.
However, Thouppuarachchi discloses compiling, a set of instructions for routing data for an execution of the complex computation [paragraph 88, “The compiler generates 1112 an instruction stream configuration based upon the determined set of arithmetic operations and set of neighbor routing connections. The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving”],
configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions [paragraphs 82, 88, 94, 78, “The compiler generates 1112 an instruction stream configuration”; “In some embodiments, the compiler assigns a routing ID to all of the inputs/outputs and neighbor connections to each ALU”; “The goal of the compiler is to, given a particular partial differential equation (or similar problem) that will be applied to all points on a 1, 2 or 3 dimensional grid, determine how to configure the computational array to compute the equation”];
executing the set of instructions using the set of programmable controllers [paragraph 25, “Each point processor comprises a computational element (e.g., an ALU) and a storage element (e.g., a register file), and is configured to receive data corresponding to a respective node of a domain and generate a value for the node for a next time step, based upon instructions received over time via an instruction stream. In some embodiments, the array of point processors is divided into slices which receive data and instructions in a staggered manner. Because all the data and computational requirements of the point processors are determined at compile time, the point processors do not need to perform any dynamic scheduling, allowing for a greater proportion of on-chip area to be allocated towards useful computation”]; and
routing data: (i) through the network [paragraphs 88, 50, 82, The compiler generates 1112 an instruction stream configuration…The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving; “the node data may be routed through successive point processors of the array to reach the particular point processor, where the routing is pre-scheduled by the compiler”; “In addition, the compiler performs routing between point processors of the computational array, in accordance with some embodiments”]; (ii) to facilitate the execution of the complex computation by the heterogenous set of computational nodes [figs. 2-3, problem package comprising the complex computation; also see fig. 10 where the compiler the compiler performs routing between point processors of the computational array to facilitate execution of the complex computation (see fig. 8 and graph on left side of fig. 10 showing complex computation)]; and (iii) in response to the execution of the set of instructions [paragraphs 88, 50, 82, The compiler generates 1112 an instruction stream configuration…The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving; “the node data may be routed through successive point processors of the array to reach the particular point processor, where the routing is pre-scheduled by the compiler”; “In addition, the compiler performs routing between point processors of the computational array, in accordance with some embodiments”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Thouppuarachchi in the method of Halpern, to implement compiling, a set of instructions for routing data for an execution of the complex computation, configuring a set of programmable controllers on the heterogenous set of computational nodes with the set of instructions; executing the set of instructions using the set of programmable controllers; and routing data: (i) through the network; (ii) to facilitate the execution of the complex computation by the heterogenous set of computational nodes; and (iii) in response to the execution of the set of instructions, in order allow for a greater proportion of on-chip area to be allocated towards useful computation [Thouppuarachchi, paragraph 25].
The modified Halpern does not explicitly a machine model of the set of links, wherein the machine model includes a bandwidth for each link in the set of links in the network.
However, Zhang discloses a machine model of the set of links, wherein the machine model includes a bandwidth for each link in the set of links in the network [Abstract, “a network control node calculates a forwarding path from a source node to a destination node”; paragraph 10, “in a process of calculating a path result and configuring a flow table shown in FIG. 1, a method for calculating a path of an SDN mainly considers external constraint conditions such as link cost (such as the number of hops), a link bandwidth and a link attribute; and after calculating a forwarding path according to an existing path algorithm, an SDN controller transmits a flow table to each OFS on the forwarding path].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Zhang in the method of the modified Halpern, to implement a machine model of the set of links, wherein the machine model includes a bandwidth for each link in the set of links in the network, in order calculate an optimal network path from the source node and the destination node with the effect of improving path calculation correctness [Zhang, paragraph 73].
Referring to claim 20, Halpern discloses a system for executing a directed graph, comprising:
a heterogenous set of computational nodes [figs. 1 and 6; paragraphs 136, 167, “Depicted accelerator tile 100 is a heterogeneous array comprised of several kinds of PEs coupled together via an interconnect network 104”; “the composition of light-weight processing elements (PE) connected by an inter-PE network”, see heterogeneous array of PEs linked together by set of links (fig. 6)];
a set of links in a network, wherein the set of links link the computational nodes in the heterogenous set of computational nodes [figs. 1 and 6; paragraphs 136, 167, “Depicted accelerator tile 100 is a heterogeneous array comprised of several kinds of PEs coupled together via an interconnect network 104”; “the composition of light-weight processing elements (PE) connected by an inter-PE network”, see heterogeneous array of PEs linked together by set of links (fig. 6)].
Halpern does not explicitly disclose a compiler configured to compile, a set of instructions for routing data for an execution of the directed graph; and
a set of programmable controllers on the heterogenous set of computational nodes configured with the set of instructions;
wherein executing the set of instructions route data through the network to facilitate the execution of the directed graph by the heterogenous set of computational nodes.
However, Thouppuarachchi discloses a compiler configured to compile, a set of instructions for routing data for an execution of the directed graph [paragraph 88, “The compiler generates 1112 an instruction stream configuration based upon the determined set of arithmetic operations and set of neighbor routing connections. The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving”; also see fig. 10 where the compiler performs routing between point processors of the computational array to facilitate execution of the complex computation (see fig. 8 and graph on left side of fig. 10 showing complex computation)];
a set of programmable controllers on the heterogenous set of computational nodes configured with the set of instructions [paragraphs 82, 88, 94, 78, “The compiler generates 1112 an instruction stream configuration”; “In some embodiments, the compiler assigns a routing ID to all of the inputs/outputs and neighbor connections to each ALU”; “The goal of the compiler is to, given a particular partial differential equation (or similar problem) that will be applied to all points on a 1, 2 or 3 dimensional grid, determine how to configure the computational array to compute the equation”];
wherein executing the set of instructions route data through the network to facilitate the execution of the directed graph by the heterogenous set of computational nodes [paragraph 25, “Each point processor comprises a computational element (e.g., an ALU) and a storage element (e.g., a register file), and is configured to receive data corresponding to a respective node of a domain and generate a value for the node for a next time step, based upon instructions received over time via an instruction stream. In some embodiments, the array of point processors is divided into slices which receive data and instructions in a staggered manner. Because all the data and computational requirements of the point processors are determined at compile time, the point processors do not need to perform any dynamic scheduling, allowing for a greater proportion of on-chip area to be allocated towards useful computation”; paragraphs 88, 50, 82, The compiler generates 1112 an instruction stream configuration…The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving; “the node data may be routed through successive point processors of the array to reach the particular point processor, where the routing is pre-scheduled by the compiler”; “In addition, the compiler performs routing between point processors of the computational array, in accordance with some embodiments”; figs. 2-3, problem package comprising the complex computation; also see fig. 10 where the compiler the compiler performs routing between point processors of the computational array to facilitate execution of the complex computation (see fig. 8 and graph on left side of fig. 10 showing complex computation)]; paragraphs 88, 50, 82, The compiler generates 1112 an instruction stream configuration…The instruction stream configuration may correspond to instructions indicating ALU operations and routing IDs for the tiles of the point processors to be pipelined between slices of the point processor array during solving; “the node data may be routed through successive point processors of the array to reach the particular point processor, where the routing is pre-scheduled by the compiler”; “In addition, the compiler performs routing between point processors of the computational array, in accordance with some embodiments”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Thouppuarachchi in the system of Halpern, to implement a compiler configured to compile, a set of instructions for routing data for an execution of the directed graph; and a set of programmable controllers on the heterogenous set of computational nodes configured with the set of instructions; wherein executing the set of instructions route data through the network to facilitate the execution of the directed graph by the heterogenous set of computational nodes, in order allow for a greater proportion of on-chip area to be allocated towards useful computation [Thouppuarachchi, paragraph 25].
The modified Halpern does not explicitly disclose using a table of bandwidth values for the set of links in the network.
However, Zhang discloses using a table of bandwidth values for the set of links in the network [Abstract, “a network control node calculates a forwarding path from a source node to a destination node”; paragraph 10, “in a process of calculating a path result and configuring a flow table shown in FIG. 1, a method for calculating a path of an SDN mainly considers external constraint conditions such as link cost (such as the number of hops), a link bandwidth and a link attribute; and after calculating a forwarding path according to an existing path algorithm, an SDN controller transmits a flow table to each OFS on the forwarding path].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Zhang in the system of the modified Halpern, to implement using a table of bandwidth values for the set of links in the network, in order to calculate an optimal network path from the source node and the destination node with the effect of improving path calculation correctness [Zhang, paragraph 73].
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Halpern, in view of Thouppuarachchi, in view of Zhang, as applied to claims 1 and 12 above, and further in view of Young et al (hereinafter Young), US 7669035 B2.
Referring to claims 5 and 15, taking claim 5 as exemplary, the modified Halpern does not explicitly disclose the method of claim 1, further comprising:
reconfiguring, during the executing, the set of programmable controllers with a second set of instructions; and
executing the second set of instructions using the set of programmable controllers.
However, Young discloses reconfiguring, during the executing, the set of programmable controllers with a second set of instructions [claim 18, “reconfigure the reconfigurable units during runtime and to coordinate the reconfigurable units in performing their respectively programmed functions”]; and
executing the second set of instructions using the set of programmable controllers [claim 18, “the reconfigurable units in performing their respectively programmed functions”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Young in the method of the modified Halpern, to implement reconfiguring, during the executing, the set of programmable controllers with a second set of instructions; and executing the second set of instructions using the set of programmable controllers, in order to provide high chip utilization throughout the chip’s operation [Young, Abstract; col. 1, lines 41-44].
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Halpern, in view of Thouppuarachchi, in view of Zhang, view of Young, as applied to claims 5 and 15 above, and further in view of Ahmed, US 20200150958 A1.
Referring to claims 6 and 16, taking claim 6 as exemplary, the modified Halpern does not explicitly disclose the method of claim 5, wherein:
routing the data is based at least in part on the execution of the second set of instructions.
However, Ahmed discloses routing the data is based at least in part on the execution of the second set of instructions [paragraph 99, the controller 310 reconfigures the routers RTs to configure the data transmission path from the prefetch engine 300 to the TPCs (00) and (10)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Ahmed in the method of the modified Halpern, to implement routing the data is based at least in part on the execution of the second set of instructions, in order to perform operations efficiently and improve transfer efficiency [Ahmed, paragraphs 4, 34].
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Halpern, in view of Thouppuarachchi, in view of Zhang, view of Young, as applied to claims 5 and 15 above, and further in view of Arimilli et al (hereinafter Arimilli), US 20040073765 A1.
Referring to claims 7 and 17, taking claim 7 as exemplary, the modified Halpern does not explicitly disclose the method of claim 5, wherein:
configuring the set of programmable controllers comprises inducing the set of programmable controllers to read from a first location in a memory; and
reconfiguring the set of programmable controllers comprises inducing the set of programmable controllers to read from a second location in the memory.
However, Arimilli discloses configuring the set of programmable controllers comprises inducing the set of programmable controllers to read from a first location in a memory [claim 1, “setting a register in each of a first and a second memory controller of the plurality of controllers that are to be reconfigured, wherein a first and a second memory module is coupled to the first and second memory controller, respectively, each register being set to indicate a current real address and a new real address for the coupled memory module”]; and
reconfiguring the set of programmable controllers comprises inducing the set of programmable controllers to read from a second location in the memory [claim 1, “setting a register in each of a first and a second memory controller of the plurality of controllers that are to be reconfigured, wherein a first and a second memory module is coupled to the first and second memory controller, respectively, each register being set to indicate a current real address and a new real address for the coupled memory module”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Arimilli in the method of the modified Halpern, to implement configuring the set of programmable controllers comprises inducing the set of programmable controllers to read from a first location in a memory; and reconfiguring the set of programmable controllers comprises inducing the set of programmable controllers to read from a second location in the memory, in order to efficiently implementing dynamic reconfiguration [Arimilli, paragraph 7].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Halpern, in view of Thouppuarachchi, in view of Zhang, as applied to claim 1 above, and further in view of Kawahito et al (hereinafter Kawahito), US 20050166195 A1.
Referring to claim 8, the modified Halpern does not explicitly disclose the method of claim 1, wherein the table of bandwidth values is generated before the compiling of the set of instructions for routing data.
However, Kawahito discloses wherein the table of bandwidth values is generated before the compiling of the set of instructions for routing data [paragraph 100, fig. 8, Specifically, if the content of the variable or storage area is set before the target program 20 is compiled, for example, zero is substituted into the variable fCalled, the set instruction generating section may generate an instruction to change the method table in accordance with the content of the variable; also see fig. 8 showing table 820 generated before compilation at 830/850].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kawahito in the method of the modified Halpern, to implement wherein the table of bandwidth values is generated before the compiling of the set of instructions for routing data, in order to increase the speed at which the target program is executed [Kawahito, paragraph 49].
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Halpern, in view of Thouppuarachchi, in view of Zhang, as applied to claim 12 above, and further in view of MOREAU-ARNOTT et al (hereinafter MOREAU-ARNOTT), US 20230267017 A1.
Referring to claim 18, the modified Halpern does not explicitly disclose the method of claim 12, wherein the machine model is configured before the set of instructions for routing data is compiled.
However, MOREAU-ARNOTT discloses wherein the machine model is configured before the set of instructions for routing data is compiled [paragraph 34, use a machine-learning model configured to route data payloads, such as a data payload of the one or more data payloads 120, through a plurality of microservices, such as one or more of Microservices 131-136 before then routing the data payloads].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of MOREAU-ARNOTT in the method of the modified Halpern, to implement wherein the machine model is configured before the set of instructions for routing data is compiled, in order to provide flexible and efficient use of network resources [Moreau-Arnott, paragraph 4].
Allowable Subject Matter
Claims 2, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims AND if the double patenting rejection is overcome.
Claims 3-4, 11, 13-14, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Farley Abad/Primary Examiner, Art Unit 2181
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