DETAILED ACTION
This office action is in response to application 19/244,187 flied 6/20/2025 that claims priority to 63/714,537 filed 10/31/2024.
Claims 1-20 have been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6-8 and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 15 recite the limitations “… identifying any write gathering buffer of the one or more write gathering buffers that is allocated to the stream identifier; identifying an unused write gathering buffer of the one or more write gathering buffers to the stream identifier …. when no write gathering buffer of the one or more write gathering buffers is allocated to the stream identifier …”
The limitation “identifying any write gathering buffer of the one or more gathering buffers that is allocated to the stream” seems to state the system looks to see if 1 or more gather buffers are allocated to the stream, and perhaps none are allocated. The limitation “identifying an unused write gathering buffer of the one or more write gathering buffers to the stream identifier” implies that at least one unused buffer is allocated to the stream “when no write gathering buffer of the one or more write gathering buffers is allocated to the stream”. This is a contradiction. The limitation “when no write gathering buffer of the one or more write gathering buffers is allocated to the stream” implies no buffers whatsoever (either used or unused) is allocated to the stream and it is unclear (given no buffers are allocated to the stream) how one would “identify an unused write gathering buffer of the one or more write gathering buffers to the stream identifier”.
Claims 7-8 and 16 are objected as being indefinite as they inherit the deficiencies of claims 6 and 15 respectively from which they depend and do not cure the deficiencies of claims 6 and 15.
Allowable Subject matter
Claims 3, 12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 3 and 12, the prior art does not teach or suggest “sending, from the write gather circuitry, a response to the interconnect for each cracked write of the gathered write burst except for a last cracked write of the transmitted gathered write burst”.
Jalal Figs. 7A and 7B and col 7 lines 43-50 through col 18 line 39 through col 22 line 67 that discloses sending a response to the interconnect for each cracked write of the gathered write burst. However, Jalal does not explicitly disclose “except for a last cracked write of the transmitted gathered write burst”.
An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitations.
Regarding claim 19, the prior art does not teach or suggest ‘where the computer-readable code designates a number of the one or more write gathering buffers in the write gather circuitry and the number is based on the number of unique write steams across the interconnect.’
This limitation bases the number of gathering buffers in the write gathering circuitry is based on the number of unique write streams across the interconnect, where the interconnect may be a PCIe interface. Thus the number of gathering buffers is based on the unique write streams across the PCIe interface. The “based on” limitation could be met by any means, such as equal to, or is proportional to, or is based on a minimum or maximum number of unique write streams. An updated search failed to identify a teaching, alone or in combination, to teach the above claim limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 9-11, 17-18, and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jalal (Jalal et al., US 11,074,206 B1).
Regarding claim 1, Jalal teaches A method (Jalal col 2 lines 33-57 teaches the inventive concepts are directed to a computer-based method) of gathering writes (Jalal col 2 lines 35-57 teaches the home node that contains a write combiner that collects/gathers writes. See also Jala Fig. 7A col 18 through col 20 line 40 that details the process of gathering writes. ) in a data processing network, (Jalal col 3 lines 10-27 discloses the inventive concepts are implemented in a network-on-chip, thus in a data processing network.)
comprising: at write gather circuitry of the data processing network: (Jalal col 2 lines 35-57 teaches the home node that contains a write combiner that collects/gathers writes. Jala Fig. 1 and col 9 line 8 discloses the embodiment may be implemented as a System on a Chip (SOC), thus is circuitry. See also Jalal Fig 7A col 18 through col 20 line 40 that discloses HN-I 204 that is a component of Coherent Interconnect where the Coherent and Write Combiner 160 together may be write gather circuitry.) gathering, in a write gathering buffer of one or more write gathering buffers of the write gather circuitry, (Consistent with Fig. 3 and [0060] of the instant application a gathering buffer is a memory that stores inbound memory requests being gathered. Jalal Fig. 1A and col 19 line 59-67 and col 22 lines 10-26 discloses the write combiner writes data as it is combined into a local register, memory, etc. where the local memory is an example of gathering buffers.) one or more cracked writes (Jalal col 7 lines 43-50 discloses the writes that are gathered are subsets (i.e. cracks per para [0003] of the instant application) of an original larger write request.) one or more streams (Jalal column 8 lines 1-25 discloses the data is part of a stream identified by a StreamID.)
transmitted across an interconnect of the data processing network (Jalal Fig. 6A col 22 lines 10-26 and col 16 line 56 through col 17 line 20 that discloses Write Combiner 160 communicates through Network Interface Controller 150 with the PCIe Device where it stores the gathered data in the local register, memory, etc..)
in accordance with a stream identifier (Jalal column 8 lines 1-25 discloses the data is part of a stream identified by a StreamID.)
until occurrence of one or more of: the last write of a stream is gathered, (Jalal col 18 lines 1-9 discloses that the steam may contain a last AXI write transaction indicator and the system write combiner stops combining write transactions after the write combiner receives the last write identifier.) the write gathering buffer fills, or the write gathering buffer is evicted for re-use; (Examiner notes that this limitation is an “or” limitation and is met when one of the or elements is identified. Examiner has provided prior art for the condition “the last write of a stream is gathered”.)
and transmitting the gathered one or more cracked writes in a gathered write burst to an external interface of the data processing network. (Jalal Figs. 7A and 7B and col 7 lines 43-50 through col 18 line 39 through col 22 line 67 that disclose the Write Combiner 160 has an End Combine that is sent to the PCIe Slave, where the combined write is 128 bytes that is a combination of two separate 64 bytes (64B) write transactions.)
Regarding claim 2, Jalal teaches the limitations of claim 1 above. Jalal further teaches further comprising labeling the write of the gathered write burst to be transmitted last as a last write of the gathered write burst. (Jalal col 18 line 1-9 discloses that the steam may contain a write element (a single crack) containing a last AXI write transaction indicator and the system write combiner stops combining write transactions after the write combiner receives the last write identifier.)
Regarding claim 9, Jalal teaches the limitations of claim 1 above. Jalal further teaches further comprising transmitting the gathered write burst to a first endpoint of the data processing network (Jalal Fig 7A col 18 through col 20 line 40 that discloses the gathered write burst is delivered to PCIe Slave 152-2 that is an example of a first endpoint.) where said transmitting include transmitting in accordance with a packetized protocol. (Jalal col 3 lines 40-55 discloses the network layer packetizes the protocol messages.)
Regarding claim 10, Jalal teaches the limitations of claim 9 above. Jalal further teaches further comprising generating the one or more cracked writes from a write burst received at a request node of the data processing network. (Jalal Fig 7A col 18 through col 20 line 40 that discloses WriteA and WriteB that are cracked writes from a AW/W (128B) write from PCIe Mater (a request node) of the data processing node that is a SOC shown in Fig. 7A hat implements the algorithm of Figs. 6A and 6B.)
Regarding claim 11, Jalal teaches A write gather circuitry (Jala Fig. 1 and col 9 line 8 discloses the embodiment may be implemented as a System on a Chip (SOC), thus is circuitry. Jalal col 2 lines 35-57 teaches the home node that contains a write combiner that collects/gathers writes. See also Jala Fig. 7A col 18 through col 20 line 40 that details the process of gathering writes.)
for a data processing network comprising: (Jalal Fig. 6A col 22 lines 10-26 and col 16 line 56 through col 17 line 20 that discloses Write Combiner 160 communicates through Network Interface Controller 150 with the PCIe Device where it stores the gathered data in the local register, memory, etc..)
one or more write gathering buffers; (Consistent with Fig. 3 and [0060] of the instant application a gathering buffer is a memory that stores inbound memory requests being gathered. Jalal Fig. 1A and col 19 line 59-67 and col 22 lines 10-26 discloses the write combiner writes data as it is combined into a local register, memory, etc. where the local memory is an example of gathering buffers.)
where the write gather circuitry is configured to receive cracked writes transmitted across an interconnect of the data processing network (Jala Fig. 6A col 22 lines 10-26 and col 16 lines 56 through col 17 line 20 the system receives Wr_DataA and Wr_DataB that are examples of cracked writes transmitted from RN-I to HN-1 which per Fig. 6B is across the Coherent Interconnect of the SOC 12 that is an example of data processing network.) from one or more data streams, (Jalal col 2 line 1-2 discloses there may be a plurality of streams)
each data stream associated with a stream identifier, (Jalal column 8 lines 1-25 discloses the data is part of a stream identified by a StreamID.)
and where a write gathering buffer of the one or more write gathering buffers is configured to: gather one or more cracked writes, (Consistent with Fig. 3 and [0060] of the instant application a gathering buffer is a memory that stores inbound memory requests being gathered. Jalal Fig. 1A and col 19 line 59-67 and col 22 lines 10-26 discloses the write combiner writes data as it is combined into a local register, memory, etc. where the local memory is an example of gathering buffers.) received at the write gather circuitry, in accordance with a stream identifier (Jalal column 8 lines 1-25 discloses the data is part of a stream identified by a StreamID.)
until occurrence of one or more of: the last write of a stream is gathered, (Jalal col 18 lines 1-9 discloses that the steam may contain a last AXI write transaction indicator and the system write combiner stops combining write transactions after the write combiner receives the last write identifier.) the write gathering buffer fills, or the write gathering buffer is evicted for re-use; and transmit the gathered one or more cracked writes in a gathered write burst to an external interface of the data processing network. (Examiner notes that this limitation is an “or” limitation and is met when one of the or elements is identified. Examiner has provided prior art for the condition “the last write of a stream is gathered”.)
Regarding claim 17, Jalal teaches the limitations of claim 11 above. Jalal further teaches
further configured to transmit the gathered write burst to a Peripheral Component Interconnect Express (PCIe) controller coupled to the write gather circuitry. (Jalal Fig 7A col 18 through col 20 line 40 that discloses the gathered write burst AW/W (128B) is transferred to a PCIE Slave )
Regarding claim 18, Jalal teaches A non-transitory computer-readable medium storing computer-readable code for fabrication of a write gather circuitry of data processing network, (Jalal col 4 lines 38-47 teaches the system contains non-transitory computer-readable medium that contains instructions that may be executed by a processor to execute the inventive concepts.)
The remainder of claim 18 recites limitations described in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 20, Jalal teaches all of the limitations of claim 18 above. Jalal further teaches where the computer-readable code designates a depth of each of the one or more write gathering buffers of the write gather circuitry and the depth of each of the one or more write gathering buffers is based on the maximum payload size settings of a controller of the data processing network. (Consistent with para [0031] of the instant application the depth of the buffers may be the size of a write request and may be based on the maximum payload size of the interface such as what is supported by the PCIe controller. Jalal col 1 lines 30-41 discloses that each write is sized to be less that the maximum transaction size supported by the interconnect.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jalal (Jalal et al., US 11,074,206 B1) as detailed in claim 1 and 11 above and further in view of Kapil (Kapil et al., US 2015/0339233 A1).
Regarding claim 4, Jalal teaches the limitations of claim 1 above. Jalal further teaches where the one or more cracked writes are generated from an external data burst, (Jalal col 7 lines 43-50 discloses the writes that are gathered are cracks (a subset) of an original larger write request.)
However, Jalal does not explicitly teach the method further comprising: marking the write gathering buffer as a child buffer when a parent write gathering buffer contains one or more cracked writes generated from a previous external data burst and having the same stream identifier; and prior to transmitting gathered write burst from the child write gathering buffer: transmitting a gathered write burst from the parent write gathering buffer.
Kapil, of a similar field of endeavor, further discloses the method further comprising: marking the write gathering buffer as a child buffer when a parent write gathering buffer contains one or more cracked writes generated from a previous external data burst and having the same stream identifier; (Kapil [0033] discloses a scatter/gather prefetch instruction which writes data values to locations specified by an array of addresses. Kapil [0039] discloses the scatter/gather instruction may include an allocation flag that specifies the allocation for the data to be written may be to prefetch data into L2 cache, a L3 cache, or both the L2 and L3 caches. Thus Kapil suggests that prefetches may be directed to the L2 cache, and when it begins to fill a subsequent prefetch request is written into the L3 cache. Consistent with para [0092] of the instant application, a parent buffer will be memory preferentially allocated and a child buffer may be allocated if the parent buffer is not available. Thus, the L2 cache is an example of a parent cache, the L3 cache is an example of a child cache. The prefetch instruction that writes a plurality of offset data as a single request is an example of an external data burst having a same stream identifier.)
and prior to transmitting gathered write burst from the child write gathering buffer: transmitting a gathered write burst from the parent write gathering buffer. (Kapil [0033], [0039], and [0042] suggests a prefetch may be directed to a L2 cache (a parent write gathering buffer), and then a second prefetch may be directed to a L3 cache (a child write gathering buffer). Thus the child write gathering buffer may be transmitted after the parent write gathering buffer (in the L2 cache).)
Jalal and Kapil are in a similar field of endeavor as both relate to gathering data that is written into a gather buffer. Thus it would have been obvious to a person of ordinary skill in the art at the effectively file date of the claimed invention to incorporate the allocation flag of Kapil that collects data into a gather buffer as taught by Kapil into the solution of Jalal that collects data into a gather buffer. Thus combining prior art elements according to known methods to yield predictable results (to enable the processor to specify the L3 cache for data to avoid cache pollution problems due to a small L2 cache size, thus enabling a processor connected to a cached memory that has knowledge of the request and the priority of the request to send high priority requests to the L2 cache that is faster and smaller, and to send lower priority requests to the L3 cache that is slower and larger than the L2 cache. Thus matching the workload to the most appropriate cache level and optimizing the cache resource usage.)
The motivation to combine Kapil into Jalal for claim 5 is the same as set forth in claim 4 above.
Regarding claim 5, Jalal and Kapil teaches all of the limitations of claim 4 above.
Jalal further teaches further comprising transmitting the gathered write burst from the external interface to an endpoint of the data processing network, including transmitting the gathered write burst over a point-to-point link. (Examiner notes that consistent with para [0002] of the instant application a PCI interface may be a point-to-point interface. Jalal Fig. 1A and 1B discloses the endpoint A may be reached across a PCIe interface, thus is connected over a point-to-point link. )
Regarding claim 13, Jalal teaches the limitations of claim 11 above.
The remainder of claim 13 recites limitations of claim 4 above and thus is rejected based on the teaching and rationale of claim 4 above.
Regarding claim 14, Jalal teaches the limitations of claim 11 above.
The remainder of claim 14 recites limitations of claim 5 above and thus is rejected based on the teaching and rationale of claim 5 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M. GIROUARD whose telephone number is (469)295-9131. The examiner can normally be reached M-F 9:30 - 7:30.
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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