DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to communication(s) filed on 06/20/2025. Claims 1-20 have been examined and are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-9, and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Il et al. KR 2025/0022523 (“Il”).
As per independent claim 1, Il teaches An apparatus (“FIG. 1 is a diagram illustrating a system including a memory device” page 3 line 36 of the attached PDF publication), comprising:
an array of memory cells (“memory device (120) may include a memory cell array (MCA, 121),” page 6 line 12 of the attached PDF publication);
a register coupled to the array of memory cells (“a second register file (703a, 703b) storing data loaded from a sub-cell block (410) of the first bank array (2080a),” page 13 lines 5-7 of the attached PDF publication);
control logic coupled to the register and the array of memory cells (“The control logic circuit (126) can include a mode register” page 7 line 38), the control logic configured to:
issue an internal command in response to a memory controller receiving an external command (“The memory controller (114) can access the memory device (120) according to a memory request of the host device (110).” Page 4 lines 40-41 of the attached PDF publication. “The control logic circuit (126) can generate control signals to perform a write operation, a read operation, a refresh operation, and/or an internal processing operation of the memory device (120) based on a command (CMD) and/or a mode selection signal (MS) received from the memory controller (114).” Page 6 lines 28-31 of the attached PDF publication);
generate an address corresponding to the internal command (“The bank control logic can generate bank control signals in response to the bank address.” Page 7 lines 29-30 of the attached PDF publication);
provide the internal command to a row decoder and a column decoder (“In response to the bank control signals, a bank row decoder corresponding to a bank address among the first to fourth bank row decoders (2060a, 2060b, 2060c, 2060d) may be activated, and a bank column decoder corresponding to a bank address among the first to fourth bank column decoders (2070a, 2070b, 2070c, 2070d) may be activated.” Page 7 lines 30-34 of the attached PDF publication);
instruct a processing unit (PU) to perform multiply accumulate (MAC) operations on received data (“the processing element (510) may include a multiply-accumulate unit.” Page 13 line 3 of the attached PDF publication).
Il does not explicitly teach instruct a processing unit.
However, Il teaches “The PIM circuit (122) of the memory device (120) may perform computational processing by the kernels offloaded by the processor(s) (112).” Page 4 lines 32-34 of the attached PDF publication.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Il with instructing a processing unit to perform multiply-accumulate operation. The motivation would be that host processor’s tasks may be offloaded to the PIM circuit which would improve the efficiency of the host processor. Page 4 lines 32-34 of the attached PDF publication.
As per dependent claim 2, Il discloses the apparatus of claim 1. Il teaches wherein the PU is a multiply accumulate (MAC) unit (“the processing element (510) may include a multiply-accumulate unit.” Page 13 line 3 of the attached PDF publication).
As per dependent claim 5, Il discloses the apparatus of claim 1. Il teaches further comprising the control logic configured to receive a read command as the external command (“The memory controller (114) can access the memory device (120) according to a memory request of the host device (110).” Page 4 lines 40-41 of the attached PDF publication. “The control logic circuit (126) can generate control signals to perform a write operation, a read operation, a refresh operation, and/or an internal processing operation of the memory device (120) based on a command (CMD) and/or a mode selection signal (MS) received from the memory controller (114).” Page 6 lines 28-31 of the attached PDF publication).
As per dependent claim 6, Il discloses the apparatus of claim 1. Il teaches further comprising the control logic configured to generate a modified read command as the internal command (“The memory controller (114) can access the memory device (120) according to a memory request of the host device (110).” Page 4 lines 40-41 of the attached PDF publication. “The control logic circuit (126) can generate control signals to perform a write operation, a read operation, a refresh operation, and/or an internal processing operation of the memory device (120) based on a command (CMD) and/or a mode selection signal (MS) received from the memory controller (114).” Page 6 lines 28-31 of the attached PDF publication).
As per dependent claim 7, Il discloses the apparatus of claim 1. Il teaches wherein a controller external to the array of memory cells issues the external command (“The bus (130) may operate in the PIM specification and/or in the HBM (High Bandwidth Memory) specification under the control of the host device (110) (e.g., the memory controller (112)).” Page 5 lines 20-22 of the attached PDF publication).
As per independent claim 8, this claim is rejected based on arguments provided above for similar rejected independent claim 1.
As per dependent claim 9, Il discloses the method of claim 8. Il teaches further comprising executing the internal command on multiple memory banks within a memory array (“Referring to FIG. 18, the memory device (120a) differs from the memory device (120) of FIG. 15 in that it further includes a second processing element (1800) in the core circuit (1810) region of each of the first to sixth banks (BANK1 to BANK6) of the core peripheral circuit structure (CPS).” Page 19 lines 26-29 of the attached PDF publication).
As per dependent claim 13, Il discloses the method of claim 8. Il teaches further comprising issuing a plurality of internal commands in response to the memory controller receiving the external command (“The control logic circuit (126) can generate control signals to perform a write operation, a read operation, a refresh operation, and/or an internal processing operation of the memory device (120) based on a command (CMD) and/or a mode selection signal (MS) received from the memory controller (114).” Page 6 lines 28-31 of the attached PDF publication).
As per independent claim 14, this claim is rejected based on arguments provided above for similar rejected independent claim 1.
As per dependent claim 15, Il discloses the apparatus of claim 14. Il teaches further comprising a respective bank control circuit coupled to each respective memory bank (“the memory device (120) may further include a clock buffer, a refresh control circuit, a voltage generation circuit, a bank control logic, etc.” Page 6 lines 38-40 and FIG. 2).
As per dependent claim 16, Il discloses the apparatus of claim 15. Il teaches wherein the respective control logic and a respective register are located within each respective bank control circuit (“the memory device (120) may further include a clock buffer, a refresh control circuit, a voltage generation circuit, a bank control logic, etc.” Page 6 lines 38-40 and FIG. 2 of the attached PDF publication).
As per dependent claim 17, Il discloses the apparatus of claim 16. Il teaches wherein each respective control logic generates a respective internal command and provides that respective internal command to a respective column decoder and a respective a row decoder coupled to a same respective memory bank (“In response to the bank control signals, a bank row decoder corresponding to a bank address among the first to fourth bank row decoders (2060a, 2060b, 2060c, 2060d) may be activated, and a bank column decoder corresponding to a bank address among the first to fourth bank column decoders (2070a, 2070b, 2070c, 2070d) may be activated.” Page 7 lines 30-34 of the attached PDF publication).
As per dependent claim 18, Il discloses the apparatus of claim 14. Il teaches further comprising the respective control logic of each respective memory bank generating and providing a respective internal command to each corresponding, respective memory bank concurrently (“In response to the bank control signals, a bank row decoder corresponding to a bank address among the first to fourth bank row decoders (2060a, 2060b, 2060c, 2060d) may be activated, and a bank column decoder corresponding to a bank address among the first to fourth bank column decoders (2070a, 2070b, 2070c, 2070d) may be activated.” Page 7 lines 30-34 of the attached PDF publication).
As per dependent claim 19, Il discloses the apparatus of claim 18. Il teaches wherein the PU is coupled to an input/output (I/O) bus (“The bus (130) may operate in the PIM specification and/or in the HBM (High Bandwidth Memory) specification under the control of the host device (110) (e.g., the memory controller (112)).” Page 5 lines 20-22 of the attached PDF publication).
As per dependent claim 20, Il discloses the apparatus of claim 19. Il teaches wherein a respective PU is coupled to a respective column decoder of each respective memory bank (“Referring to FIG. 2, the memory device (120) may include an address buffer (210), a control logic circuit (126), a row decoder (2060), a column decoder (2070), a memory cell array (121), a sense amplifier (2082), a PIM circuit (122), an input/output gating circuit (2090), and a data input/output buffer (2095). Although not shown in FIG. 2, the memory device (120) may further include a clock buffer, a refresh control circuit, a voltage generation circuit, a bank control logic, etc.” Page 6 lines 35-40 and FIG. 2 of the attached PDF publication).
Claims 3-4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Il in view of Condemi et al. US 2002/0126563 (“Condemi”).
As per dependent claim 3, Il discloses the apparatus of claim 1. Il may not explicitly disclose, but in an analogous art in the same field of endeavor, Condemi teaches wherein the register is coupled to a counter (“On the bank EVEN_BANK, the current address is pointed by a standard binary counter EVEN_COUNTER, while on the other bank ODD_BANK the address is pointed by a register ODD_REGISTER in which the content of the binary counter of the bank EVEN_BANK is copied as it is produced.” Para 0019).
Given the teaching of Condemi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Il with “wherein the register is coupled to a counter”. The motivation would be that the hardware is simplified, para 0020 of Condemi, and as a result cost is reduced.
As per dependent claim 4, Il in combination with Condemi discloses the apparatus of claim 3. Il may not explicitly disclose, but Condemi teaches further comprising the counter configured to increment the address, wherein the address stored in the register (“the counter EVEN_COUNTER is incremented,” para 0017).
The same motivation that was utilized for combining Il and Condemi as set forth in claim 3 is equally applicable to claim 4.
As per dependent claim 11, this claim is rejected based on arguments provided above for similar rejected dependent claim 4.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Il in view of Bains US 2015/0092508 (“Bains”).
As per dependent claim 10, Il discloses the method of claim 8. Il may not explicitly disclose, but in an analogous art in the same field of endeavor, Bains teaches further comprising incrementing an address in the control logic in response to the PU executing the internal command (“the memory device increments a row address counter only when the per bank refresh counter is reset. The memory device receives a per bank refresh command from an associated memory controller, and performs a per bank refresh in response to receiving the per bank refresh command.” Para 0013).
Given the teaching of Bains, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Il with “further comprising incrementing an address in the control logic in response to the PU executing the internal command”. The motivation would be that the memory controller can perform some of the refresh operations in the background, para 0012 of Bains, which would improve the performance of the memory device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Il in view of Condemi and in further view of Bains.
As per dependent claim 12, Il in combination with Condemi discloses the method of claim 11. Il and Condemi may not explicitly disclose, but in an analogous art in the same field of endeavor, Bains teaches further comprising storing a subsequent address corresponding to a subsequent internal command in the register in response to an address incrementing (“The memory device increments the per bank refresh counter in response to receiving the per bank refresh command, and increments the row address counter when the per bank refresh counter is reset, either by rolling over or by a reset condition.” Para 0013).
Given the teaching of Bains, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Il and Condemi with “further comprising storing a subsequent address corresponding to a subsequent internal command in the register in response to an address incrementing”. The motivation would be that the memory controller can perform some of the refresh operations in the background, para 0012 of Bains, which would improve the performance of the memory device.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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