DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 20 June 2025.
Claims 1-20 are pending and have been presented for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-9 and 20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12,360,892. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are anticipated by the claims of the ‘892 patent as shown below.
Regarding claim 20 of the instant application: the method performed by claim 20 is anticipated by the storage device of claim 1 of the ‘892 patent as the storage device is configured to perform the same steps as the claimed method.
12,360,892
19/244,323
1. A storage device comprising:
(A) a nonvolatile memory device comprising a plurality of memory cells; and a controller configured to perform a write operation on at least one write unit included in the plurality of memory cells, and to perform an erase operation on at least one erase unit included in the plurality of memory cells,
(A) wherein the controller comprises an internal buffer including zone buffers, and is further configured to:
allocate a plurality of zones to a storage space of the nonvolatile memory device based on a request received from an external host device, select two or more erase units from among a plurality of erase units included in the plurality of memory cells to be allocated to each zone of the plurality of zones based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones,
(B) based on reads for sequential logical addresses being requested by the external host device,
(C) read first data corresponding to the sequential logical addresses from the nonvolatile memory device, and output the first data to the external host device,
(D) and based on the reads being requested: determine next sequential addresses without receiving a next read request from the external host device,
(E) determine at least one zone to which the next sequential addresses belong, and based on at least one feature corresponding to the at least one zone, perform a prefetch operation by reading second data corresponding to the next sequential logical addresses from the nonvolatile memory device,
(F) and storing the second data in the internal buffer.
1. A storage device comprising:
(A) a nonvolatile memory device comprising a plurality of memory cells; and a controller comprising an internal buffer, and configured to:
(B) based on receiving a plurality of read requests corresponding to sequential logical addresses from an external host device,
(C) read first data corresponding to the sequential logical addresses from the nonvolatile memory device, and output the first data to the external host device,
(D) and based on the plurality of read requests: determine next sequential logical addresses without receiving a next read request from the external host device,
(E) and based on at least one feature corresponding to the next sequential logical addresses, perform a prefetch operation by reading second data corresponding to the next sequential logical addresses from the nonvolatile memory device,
(F) and storing the second data in the internal buffer.
Claims 2/3/4/5/6/7/8/9
Claims 2/3/4/5/6/7/8/9
1. A storage device comprising: a nonvolatile memory device comprising a plurality of memory cells;
(A) and a controller configured to perform a write operation on at least one write unit included in the plurality of memory cells, and to perform an erase operation on at least one erase unit included in the plurality of memory cells,
(A) wherein the controller comprises an internal buffer including zone buffers, and is further configured to: allocate a plurality of zones to a storage space of the nonvolatile memory device based on a request received from an external host device, select two or more erase units from among a plurality of erase units included in the plurality of memory cells to be allocated to each zone of the plurality of zones based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones,
(B) based on reads for sequential logical addresses being requested by the external host device,
(C) read first data corresponding to the sequential logical addresses from the nonvolatile memory device,
(D) and output the first data to the external host device,
(E) and based on the reads being requested: determine next sequential addresses without receiving a next read request from the external host device,
(F) determine at least one zone to which the next sequential addresses belong, and based on at least one feature corresponding to the at least one zone, perform a prefetch operation by reading second data corresponding to the next sequential logical addresses from the nonvolatile memory device,
(G) and storing the second data in the internal buffer.
20. A method of managing a storage device,
(A) the method being performed by a controller and comprising:
(B) based on receiving a plurality of read requests corresponding to sequential logical addresses from an external host device,
(C) reading first data corresponding to the sequential logical addresses from a nonvolatile memory device;
(D) outputting the first data to the external host device;
(E) based on the plurality of read requests: determine next sequential logical addresses without receiving a next read request from the external host device,
(F) and based on at least one feature corresponding to the next sequential logical addresses, performing a prefetch operation by reading second data corresponding to the next sequential logical addresses from the nonvolatile memory device,
(G) and storing the second data in an internal buffer included in the controller.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 8, 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over FELD (U.S. Patent Application Publication #2023/0325090) in view of LEE (U.S. Patent Application Publication #2023/0168827).
1. FELD discloses A storage device comprising: a nonvolatile memory device comprising a plurality of memory cells (see [0035]-[0036]: storage device including a non-volatile memory such as flash); and a controller (see [0035]: storage processing circuitry) comprising an internal buffer (see LEE below), and configured to: based on receiving a plurality of read requests corresponding to sequential logical addresses from an external host device (see [043]: read request from host; [0044]: determination that the host reads are part of a sequential read stream), read first data corresponding to the sequential logical addresses from the nonvolatile memory device (see [0043]: read data is retrieved from the nonvolatile memory and stored in cache), and output the first data to the external host device (see [0039]: servicing read requests using data in the cache reduces latency for the host, this implies the data is being output to the host), and based on the plurality of read requests: determine next sequential logical addresses without receiving a next read request from the external host device (see [0044]: prefetch distance specifies how far ahead, in terms of addresses, a prefetch operation will be performed), and based on at least one feature corresponding to the next sequential logical addresses (see [0044]: maximum distance value), perform a prefetch operation by reading second data corresponding to the next sequential logical addresses from the nonvolatile memory device (see [0044]: additional data is pre-fetched from memory based on the average I/O size, the distance is how far ahead from the last read from the host data is fetched – this is the data that the system has not received a read request for), and storing the second data in the internal (see LEE below) buffer (see [0043]: data is stored in a cache).
LEE discloses the following limitations that are not taught by FELD: a controller with an internal buffer (see [0069]-[0070]: memory may be disposed within the controller, or external to the controller) and storing data in the internal buffer (see [0070]: memory can store data pertaining to read or write operations). FELD already discloses storing data in a cache by the controller, but fails to disclose the cache being internal to the controller. Implementing a buffer internal to a controller is a matter of design choice, as there are a limited number of well-known solutions for including a buffer with a memory controller. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FELD to have the cache be internal to the controller, as disclosed by LEE. One of ordinary skill in the art would have been motivated to make such a modification as this would have been obvious to try, as shown by LEE. FELD and LEE are analogous/in the same field of endeavor as both references are directed to storage systems.
8. The storage device of claim 1, wherein the controller is further configured to perform the prefetch operation based on a number of the plurality of read requests being greater than or equal to a threshold value (see FELD [0043]: more than one read address).
9. The storage device of claim 1, wherein the controller is further configured to: receive a second plurality of read requests from the external host device, wherein the second plurality of read requests correspond to logical addresses which are not sequential with the sequential logical addresses, and discard the second data based on a number of the second plurality of read requests being greater than or equal to a threshold value (see FELD [0042]: wasted pre-fetch; this is data that is not accessed by subsequent read requests, indicating the subsequent read requests were not sequential to the plurality of read requests the data is eventually evicted, which is considered as being discarded).
20. FELD discloses A method of managing a storage device (see [0035]-[0036]: storage device including a non-volatile memory such as flash), the method being performed by a controller (see [0035]: storage processing circuitry) and comprising: based on receiving a plurality of read requests corresponding to sequential logical addresses from an external host device (see [043]: read request from host; [0044]: determination that the host reads are part of a sequential read stream), reading first data corresponding to the sequential logical addresses from a nonvolatile memory device (see [0043]: read data is retrieved from the nonvolatile memory and stored in cache), and outputting the first data to the external host device (see [0039]: servicing read requests using data in the cache reduces latency for the host, this implies the data is being output to the host), based on the plurality of read requests: determine next sequential logical addresses without receiving a next read request from the external host device (see [0044]: prefetch distance specifies how far ahead, in terms of addresses, a prefetch operation will be performed), and based on at least one feature corresponding to the next sequential logical addresses (see [0044]: maximum distance value), performing a prefetch operation by reading second data corresponding to the next sequential logical addresses from the nonvolatile memory device (see [0044]: additional data is pre-fetched from memory based on the average I/O size, the distance is how far ahead from the last read from the host data is fetched – this is the data that the system has not received a read request for), and storing the second data in an internal (see LEE below) buffer (see [0043]: data is stored in a cache), included in the controller (see [0035]: storage processing circuitry).
LEE discloses the following limitations that are not taught by FELD: a controller with an internal buffer (see [0069]-[0070]: memory may be disposed within the controller, or external to the controller) and storing data in the internal buffer (see [0070]: memory can store data pertaining to read or write operations). FELD already discloses storing data in a cache by the controller, but fails to disclose the cache being internal to the controller. Implementing a buffer internal to a controller is a matter of design choice, as there are a limited number of well-known solutions for including a buffer with a memory controller. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FELD to have the cache be internal to the controller, as disclosed by LEE. One of ordinary skill in the art would have been motivated to make such a modification as this would have been obvious to try, as shown by LEE. FELD and LEE are analogous/in the same field of endeavor as both references are directed to storage systems.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over FELD (U.S. Patent Application Publication #2023/0325090) and LEE (U.S. Patent Application Publication #2023/0168827) as applied to claims 1, 8, 9 and 20 above, and further in view of NATHELLA (U.S. Patent Application Publication #2022/0413866).
10. The storage device of claim 1 (see FELD above), wherein the controller is further configured to set a parameter for the prefetch operation based on a set request received from the external host device (see NATHELLA below).
NATHELLA discloses the following limitations that are not disclosed by FELD: the controller is further configured to set a parameter for the prefetch operation based on a set request received from the external host device (see [0021]-[0022]: prefetch control circuity uses address-range parameters from the range prefetch instruction to configure the prefetching). A user programmer uses the range prefetch instruction, which is sent by the host when executing the program (see [0023]). Allowing a user to specify the parameters for a prefetch operation can provide a better balance between prefetch coverage and power consumption (see [0026]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify FELD to set a parameter for prefetching, as disclosed by NATHELLA. One of ordinary skill in the art would have been motivated to make such a modification to provide a better balance between coverage and power consumption, as taught by NATHELLA. FELD and NATHELLA are analogous/in the same field of endeavor as both references are directed to prefetching.
11. The storage device of claim 10, wherein the parameter for the prefetch operation indicates at least one feature used to determine whether to perform the prefetch operation (see NATHELLA [0021]: stride parameter, specified ranges of address).
Allowable Subject Matter
Claims 12-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the limitations of claims 2-7 and 12-19 are commensurate in scope with the allowable subject matter identified in the parent application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MATSUDA [2023/0289080] discloses creating zones in a non-volatile memory system. [0031]-[0057]
MUTHIAH [2022/0083256] discloses a zoned namespace and prefetching of data. [0064]
JIN [2021/0056023] discloses an internal buffer in the controller, multiple buffers, each buffer corresponding to a range of addresses. [0095]-[0103]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/ Primary Examiner, Art Unit 2132
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