Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show claim 14. the display apparatus of claim 12, further comprising a second shielding layer under the plurality of transistors in the stage circuit block.as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Examiner was unable to locate claim 14. the display apparatus of claim 12, further comprising a second shielding layer under the plurality of transistors in the stage circuit block.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pang et al 2021/0098737 hereinafter, Pang in view of CN10826954, hereinafter, ‘540.
In regards to claim 1, Pang teaches a display apparatus, comprising (abstract):
a substrate including a display area having a plurality of sub-pixels and non-display area surrounding the display area (fig. 5 111);
a driving transistor and a capacitance in each sub-pixel, the driving transistor including an active layer, a gate electrode, a source electrode, and a drain electrode, and the capacitance including a first electrode and a second electrode (figs.4 and 5 (210 and 220 [0057-0065]);
a first shielding layer under the driving transistor (fig. 5 (205));
an interlayer insulating layer on the second electrode (fig. 4 and 5 (240) and SL);
an overcoat layer in the non-display area (fig. 5 (290 and NDA); and
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a stage circuit block (fig. 2 (120)) and
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542
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Pang fails to teach a plurality of clock signal lines.
However, ‘540 teaches plurality of clock signal lines (fig. 1 121 and 114).
A shift register and a display device including the shift register. A shift register and a display device including the shift register are disclosed in which the size of the circuit is reduced. The shift register includes a stage that outputs a gate shift clock supplied through a gate shift clock line as a scan pulse and outputs a carry shift clock supplied through a carry shift clock line as a carry pulse. The carry shift clock line overlaps the gate shift clock line.(abstract)
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Pang to further include plurality of clock signal lines in order to decrease bezel size (last para of background)
Therefore, Pang in view of ‘540 teaches
wherein each of the clock signal lines includes a first clock signal line and a second clock signal line (fig. 1 (121 and 114) ‘540 and
wherein the first clock signal line is disposed on the same layer as the first shield electrode and the second clock signal line is disposed on the interlayer insulating layer. (fig. 4 and 5 (240) and SL) (figs.4 and 5 (210 and 220 [0057-0065]) ‘540.
In regards to claim 2, Pang and ‘540 teaches the display apparatus of claim 1, wherein the capacitance further includes a third electrode on the interlayer insulating layer(fig. 5 222/221) Pang.
In regards to claim 3, Pang and ‘540 teaches display apparatus of claim 1, wherein the clock signal lines are disposed closer to an edge of the substrate than the stage circuit block.(fig. 1 and 2 traces fan out to edge and shift register closer to display) ‘540
In regards to claim 4, Pang and ‘540 teaches display apparatus of claim 1, wherein the source electrode and the drain electrode are disposed on the same layer as the gate electrode (fig. 5 213, 212 and 214 are on the same layer) Pang.
In regards to claim 5, Pang and ‘540 teaches display apparatus of claim 1, wherein the source electrode and the drain electrode are disposed on the active layer. (fig. 5 (282) [0068-0075] Pang.
In regards to claim 6, Pang and ‘540 teaches display apparatus of claim 1, further comprising a light emitting layer in each sub-pixel (fig. 5 source and drain electrode and 211) [0068-0075] Pang.
In regards to claim 7, Pang and ‘540 teaches display apparatus of claim 6, wherein the light emitting layer includes: a pixel electrode connected to the driving transistor; a light emitting layer on the pixel electrode; and a cathode electrode on the light emitting layer. (fig. 5 (282) [0068-0075] Pang
In regards to claim 8 Pang and ‘540 teaches display apparatus of claim 1, further comprising a plurality of low potential voltage lines and a plurality of high potential voltage lines [0047] Pang (fig. 3 (631 632, and 633) ‘540.
Claim(s) 9-11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pang in view of ‘540 further in view of Jin et al 2018/0301520 hereinafter, Jin.
In regards to claim 9, Pang and ‘540 fail to teach the display apparatus of claim 8, wherein the plurality of low potential voltage lines are disposed between the stage circuit block and the display area and the plurality of high potential voltage lines are disposed between the stage circuit block and the clock signal lines.
However, Jin teaches the power line between the shift register and driving circuit wires (fig. 2 (321) between display and 550)[0057]
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Pang and ‘540 to further include wherein the plurality of low potential voltage lines are disposed between the stage circuit block and the display area and the plurality of high potential voltage lines are disposed between the stage circuit block and the clock signal lines as taught by Jin in order to a uniform power source around the display which can provide for even brightness.
In regards to claim 10, Pang and ‘540 in view of Jin teaches display apparatus of claim 9, wherein the clock signal lines, the low potential voltage lines, and the low potential voltage lines are respectively extended in a first direction.(fig. 3 631, 632, and 633) ‘540
In regards to claim 11, Pang and ‘540 in view of Jin display apparatus of claim 10, wherein the plurality of clock signal lines are arranged in a second direction perpendicular to the first direction to supply clock signal to the stage circuit block from outside (fig. 3 lines extending to st1, etc) ‘540).
In regards to claim 17,see rational of claim 9, Pang and ‘540 in view of Jin display apparatus of claim 1, further comprising an encapsulation layer in the display area and the non-display area.(fig. 4 112 in NDA and [0044]) Pang
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pang in view of ‘540 and Jin further in view of Oh et al 2016/0087237 hereinafter, Oh
In regards to claim 18, Pang and ’540 and Jin fail to teach the display apparatus of claim 17, wherein the encapsulation layer includes a first encapsulation layer made of an insulating material and a second encapsulation layer made of a metal.
However, Oh teaches wherein the encapsulation layer includes a first encapsulation layer made of an insulating material and a second encapsulation layer made of a metal. [0016, 116-117].
It would have been obvious to one of ordinary skill in art to modify the teachings of Pang and ‘540 to further include wherein the encapsulation layer includes a first encapsulation layer made of an insulating material and a second encapsulation layer made of a metal as taught by Oh in order to provide simple substitution of one known encapsulation layer for another and the results would have been predictable at protecting the display.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pang in view of ‘540 further in view of Lim et al (2020/0193911) hereinafter, Lim.
In regards to claim 12, Pang and ‘540 fails to teach the display apparatus of claim 1, wherein the stage circuit block includes a plurality of transistors.
However, Lim teaches wherein the stage circuit block includes a plurality of transistors.(fig. 3 shift register and fig. 4 T2, T3, etc Lim).
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It would have been obvious to one of ordinary skills in the art to modify the teachings of Pang and ‘540 to further include wherein the stage circuit block includes a plurality of transistors as taught by Lim in order to include switching on and off of the shift signals.
In regards to claim 13, Pang and ‘540 in view of Lim teaches display apparatus of claim 12, wherein each of the transistors has a same structure as the driving transistor on the same layer (fig. 4 source and drain and gate for transistors) Lim.
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pang in view of ‘540 and Lim further in view of Sawada et al (2015/0301415) hereinafter, Sawada.
In regards to claim 14. Pang and ‘540 fail to teach the display apparatus of claim 12, further comprising a second shielding layer under the plurality of transistors in the stage circuit block.
However, Sawada teaches further comprising a second shielding layer under the plurality of transistors in the stage circuit block. (fig. 6 136, 135).Sawada
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Pang and ‘540 to further include further comprising a second shielding layer under the plurality of transistors in the stage circuit block as taught by Sawada in order to suppress light leakage [0006].
In regards to claim 15, Pang and ‘540 in view of Sawada teaches display apparatus of claim 14, wherein the second shielding layer is disposed on the same layer as the first shielding layer. (fig. 6 136, 135).Sawada
Allowable Subject Matter
Claim 16,and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRANT SITTA whose telephone number is (571)270-1542. The examiner can normally be reached M-F 7:30-4:00.
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/GRANT SITTA/Primary Examiner, Art Unit 2622
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