Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status: Please all the replies and correspondence should be addressed to Examiner’s art unit 2629. Receipt is acknowledged of papers submitted on 06-20-2025 under new application being continuation parent application # 18,639,733 filed on 04/18/2024, matured to Patent # 12,367,634 , which is continuation of parent application # 17,680,947 filed on 02/03/2022, matured to Patent # 11,989,816; which have been placed of record in the file. Claims 1-18 are pending.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 in parent application # 18,639,733 filed on 04/18/2024, matured to Patent # 12,367,634 and parent application # 17,680,947 filed on 02/03/2022, matured to Patent # 11,989,816
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged. Applicant has complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. with a specific reference to the prior-filed application in compliance with 37 CFR 1.78(a) is included in the first sentence(s) of the specification following the title or in an application data sheet. Applicant has also included claiming under 35 U.S.C. 120, 121 or 365(c), the relationship (i.e., continuation, divisional, or continuation-in-part) of the applications. However, Applicant has recited status (abandoned, patented or co-pending) of the parent application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06-20-2025, 05-18-2026, 07-06-2026, 07-23-2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-18 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,367,634 B2 and claims 1-14 of U.S. Patent No. 11,989,816 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows: Comparison of Instant application Claims 1-18 to over claims 1-18 of U.S. Patent No. 12,367,634 B2 and claims 1-14 of U.S. Patent No. 11,989,816 B2 as follows:
Instant US Application Number
19,244,367
US Patent Number
US 12,367,634 B2
US 11,989,816 B2
1. A method of managing resources in a graphics processing pipeline, the method comprising :in response to selecting a task for execution within a texture / shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers for a first phase of the task, wherein the task executes a program comprising a plurality of phases; and when the task reaches a boundary between two phases, freeing only the dynamic allocation of temporary registers.
US 12,367,634 B2
1. A method of managing resources in a graphics processing pipeline, the method comprising: in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers for a first phase of the task, wherein the task executes a program comprising a plurality of phases; and when the task reaches a boundary between two phases, freeing the dynamic allocation of temporary registers, wherein the static allocation of temporary registers is not freed until the task has completed execution.
US 11,989,816 B2
1. A method of managing resources in a graphics processing pipeline, the method comprising: in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers for a first phase of the task only, wherein the task executes a program comprising a plurality of phases and wherein the static allocation of temporary registers comprises any temporary registers that are live at a boundary between two phases; and when the task reaches a boundary between two phases, freeing the dynamic allocation of temporary registers and allocating to the task a new dynamic allocation of temporary registers for a next phase of the task, wherein the static allocation of temporary registers is not freed until the task has completed execution.
Please note the comparison of independent claim 1 of instant application, to Claim 1 of U.S. Patent No. 12,367,634 B2 and Claim 1 of U.S. Patent No. 11,989,816 B2 to avoid 101 statutory double patenting rejections the claims limitation by curtailing the details and language has been changed. However, instant application independent claim limitations are described in independent claims of the parent applications. They both are merely claiming same “A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task”.
Further Claims 2-18 of the instant application maps to 2-18 of the patent #12,367,634 which further suggests 2-18 are same or similar to 2-18. Claims 2-18 of the instant application maps to claims 1-7 and 10-14 of the patent #11,989,816 respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant is requested to review cited prior arts on USPTO 892’s.
Prior art of HEINRICH Steven James et al. (US 20110078381 A1) disclosure, paras. 20-116, discloses, A method for managing a parallel cache hierarchy in a processing unit. The method including receiving an instruction that includes a cache operations modifier that identifies a level of the parallel cache hierarchy in which to cache data associated with the instruction; and implementing a cache replacement policy based on the cache operations modifier. An architecture that offers massively parallel threaded processors with multiple cache hierarchies. Strategies for making efficient use of the memory hierarchy are useful for high performance operation, especially to maximize utility of the caches closest to the processors. The L1» Cache Unit (also referred to as the "L1 cache" or simply "L1") includes a set-associative first level data cache with a number of operations and polices for that purpose. The L1» cache may service multiple clients, of which the primary one may be a multithreaded streaming multiprocessor (SPM). The SPM requests are combined from multiple parallel execution threads. Other clients may include an M-Pipe Controller (MPC) and a Primitive Engine (PE). Selected operations and polices are summarized below followed by a more detailed description, including (i) classification of allocation/replacement policies by request type and cache op, (ii) one-clock invalidate-all by type, and (iii) last-use invalidate-all. An architecture that offers massively parallel threaded processors with multiple cache hierarchies. Strategies for making efficient use of the memory hierarchy are useful for high performance operation, especially to maximize utility of the caches closest to the processors. The L1» Cache Unit (also referred to as the "L1 cache" or simply "L1") includes a set-associative first level data cache with a number of operations and polices for that purpose. The L1» cache may service multiple clients, of which the primary one may be a multithreaded streaming multiprocessor (SPM). The SPM requests are combined from multiple parallel execution threads. Other clients may include an M-Pipe Controller (MPC) and a Primitive Engine (PE). Selected operations and polices are summarized below followed by a more detailed description, including (i) classification of allocation/replacement policies by request type and cache op, (ii) one-clock invalidate-all by type, and (iii) last-use invalidate-all.
The prior art of Jiao Yang et al. (US 20070091089 A1) disclosure, paras. 29-90, disclosing, methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked. The execution units of a pool of execution units are individually scheduled to perform shader-related computations, such that a given execution unit can be scheduled over time to perform shader operations for different shader stages. As prior art systems employ dedicated shader hardware, such a dynamic and robust thread assignment was not implemented or realized. A novel system and method for performing effective load balancing of a pool of execution units among several shader stages in a graphics pipeline. In embodiments described above a two-level scheduling is performed, whereby a first level scheduling is performed at the thread level (e.g., assigning certain threads within a given execution unit to perform certain tasks) and a second level scheduling is performed on an execution unit level (e.g., assigning certain execution units to certain shader stages). The second level scheduling can be static (e.g., controlled by the software driver) or dynamic (e.g., controlled in real time by graphics hardware). Further still, embodiments have been described which detail various methodologies for performing the dynamic scheduling. One methodology implements what was described as a load balancing scheduling (scheduled based on a workload balancing). The scheduling/allocation based on a calculation of instruction throughput (or drain rate).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRABODH M DHARIA whose telephone number is (571)272-7668. The examiner can normally be reached Monday -Friday 9:00 AM to 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached on 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any response to this action should be mailed to:
Commissioner of Patents and Trademarks
P.O. Box 1450
Alexandria VA 22313-1450
/Prabodh M Dharia/
Primary Examiner
Art Unit 2629
08-03-2026
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