DETAILED ACTION
The following claims are pending in this office action: 1-20
Claims 1 and 14 are independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings filed on 06/20/2025 are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 5, 14, 16 and 17 are rejected under 35 U.S.C. §103 as being unpatentable over ELKOUSS et al.( WO 2023244105 A1)[hereinafter “ELKOUSS”] in view of Walenta et al. (New Journal of Physics 16 (2014) 013047) [hereinafter “Walenta”] and view of Aldereguia et al (US 9094162 B2) [hereinafter “Aldereguia”] and further in view of ANDERSON et al. (EP 0306196 A2) [hereinafter “ANDERSON”].
As per claim 1, ELKOUSS discloses a device, comprising:
at least one processor; and
a memory coupled to the at least one processor with instructions stored thereon, wherein the instructions, when executed by the at least one processor, enable the device to:
obtain Quantum Key Distribution (QKD) data,( ELKOUSS, [col.3 ln30-33]” the method comprising quantum key distribution (QKD) for distributing a raw key of length N between at least a first and a second party, the method comprising the second party: - receiving the raw key through a quantum channel;”).
divide the QKD data into a set of data blocks, ( ELKOUSS, [ln]” Both Alice and Bob now split the received raw key in strings or words of length n with n smaller than N.”) wherein each data block of the set of data blocks of the device corresponds to a data block of a remote device, ( ELKOUSS, [col.13 ln5-10]” the secure key can be shared. Alternatively, as illustrated in figure 1, a third party is connected via a quantum channel with both Alice and to Bob, and other parties if needed. In this way, a raw key of length N is shared or disseminated”)
determine, based on a Bit Error Rate (BER) or a Signal to Noise Ratio (SNR), an error correction code, ( ELKOUSS, [col.2 ln15-20]” the device further obtains an initial error correction codeword; determines, based on a Signal to Noise Ratio (SNR) and/or Bit Error Rate (BER) of the QKD data,”)
perform an error correction step, ( ELKOUSS, [claim 1]” processing the small words using an error correction code based upon the small words of length n;”) comprising:
performing decoding on each data block of a first input set of data blocks( ELKOUSS, [claim 1 and claim 16]” processing the small words including applying a correction code on the small words and the encoded information from the transmissions from the first party;” and “the first party receiving from the second party through the public classical channel a series of transmissions, each transmission comprising encoded information”) based on the error correction code( ELKOUSS, [col.3 ln5-10]” Each word is error-corrected…) and based on remote error correction information, ( ELKOUSS, [ln30-32]” for each block, i.e. for i = 1 to m, do a. Alice sends s(x.sup.1), i.e. the syndrome of block x.sup.1, to Bob through a classical channel. ”).
and perform an error detection step, ( ELKOUSS, [col.20 ln5-10]” identifying incorrectly corrected small words using the information from the N/n transmissions from….”) comprising:
ELKOUSS does not disclose
wherein the error correction code is configured such that a code rate of the error correction code is larger than a Shannon capacity for noise exhibited by the QKD data, or that the error correction code, after decoding the QKD data, leaves errors in corrected QKD data with a probability of at least 98%,
generating a first output set of data blocks based on the decoding,
computing local error detection information on each data block of a second input set of data blocks, and
generating a second output set of data blocks based on the local error detection information and based on remote error detection information, wherein
the error correction step and the error detection step are performed in any order, and
in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks, and
in response to the error detection step being performed before the error correction step, the second input set of data blocks comprises the set of data blocks of the device and the first input set of data blocks comprises the second output set of data blocks.
However, Walenta discloses
wherein the error correction code is configured such that a code rate of the error correction code(Walenta, [Para 2.4]” The LDPC code rate, i.e. the fraction of unpublished information, can be set to fEC (Q) 2 {1/2, 2/3, 3/4, 5/6} to adapt to the expected error rates.”) is larger than a Shannon capacity for noise exhibited by the QKD data, or [that the error correction code, after decoding the QKD data, (Walenta, [Para 2.4]” Alice performs syndrome decoding and checks the parity”)leaves errors in corrected QKD data Walenta, [Para 2.4]” However, there is still a certain probability that uncorrected errors remain after error correction, especially for error rates larger than 6% (see figure 3, left).”) with a probability of at least 98%], (Walenta, [Para 2.4]” Figure 3. (left) Measurement results for different code rates showing the probability that the comparison between Alice and Bob’s verification hash tags indicates at least one remaining error per 2048 bit block of error corrected keys.” The Examiner interprets figure 3 (left) as showing a probability of approximately 0.98 or greater that at least one error remains in an error-corrected key block.).
generating a first output set of data blocks based on the decoding, (Walenta, [Para 2.4]” Alice performs syndrome decoding and checks the parity. If an error occurred, the corresponding block is discarded”).
computing local error detection information on each data block of a second input set of data blocks, (Walenta, [Para 2.4]” The checksums are generated using polynomial hashing [3, 4], with a new random 48-bit seed for each checksum…For each block, the hash, as well as the random choice of hash function, is sent to Alice.”) and
generating a second output set of data blocks based on the local error detection information (Walenta, [Para 2.4]” To detect remaining errors, we implement a subsequent verification step, where Bob transmits a 48-bit hash checksum per LDPC code block to Alice”)and based on remote error detection information, (Walenta, [Para 2.4, 2.5]” For each block, the hash, as well as the random choice of hash function, is sent to Alice. If a checksum mismatch occurs, the associated block is discarded” and “Once we obtain 512 blocks of 1944 error corrected and verified bits, Alice compares them with her original random bit sequence”).
Therefore it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify ELKOUSS to include wherein the error correction code is configured such that a code rate of the error correction code is larger than a Shannon capacity for noise exhibited by the QKD data, or that the error correction code, after decoding the QKD data, leaves errors in corrected QKD data with a probability of at least 98%, generating a first output set of data blocks based on the decoding, computing local error detection information on each data block of a second input set of data blocks, and generating a second output set of data blocks based on the local error detection information and based on remote error detection information as suggested by Walenta. One of ordinary skill in the art would have been motivated to do so because incorporating Walenta’s error correction and verification techniques would improve the reliability of the QKD key-generation process by correcting errors in the sifted key and subsequently detecting and discarding blocks containing residual errors, thereby reducing the likelihood that erroneous key material is retained.
The combination of ELKOUSS and Walenta fails to disclose
the error correction step and the error detection step are performed in any order, and
in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks, and
in response to the error detection step being performed before the error correction step, the second input set of data blocks comprises the set of data blocks of the device and the first input set of data blocks comprises the second output set of data blocks.
However Aldereguia in the same field of endeavor discloses
the error correction step and the error detection step are performed in any order (Aldereguia, [col.5 ln 15-23]” If the word does not include a parity error, the method of FIG. 2 continues by committing (214) the word. The method of FIG. 2 continues by determining (206) whether only one word includes a parity error. If only one word of the block includes a parity error the method of FIG. 2 continues by correcting (210) the one word that includes the parity error through use of the ECC of the block and committing (212) the corrected word.”).
in response to the error detection step being performed before the error correction step, (Aldereguia, [col.5 ln 15-20]” determining (206) whether only one word includes a parity error… correcting (210) the one word that includes the parity error through use of the ECC of the block”) the second input set of data blocks comprises the set of data blocks of the device(Aldereguia, [col.5 ln 35-37]” receiving (202) a block of data; determining (204) whether a word of the block includes a parity error;”) and the first input set of data blocks comprises the second output set of data blocks. (Aldereguia, [col.5 ln 15-21, col.6 ln 10-15, col.6 ln14-20]” If only one word of the block includes a parity error the method of FIG. 2 continues by correcting (210) the one word that includes the parity error through use of the ECC of the block” and “ The receiver identifies a parity error in only the second byte” and then “The receiver may then correct (210) the second byte…”).
Therefore it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify ELKOUSS to include wherein the error correction code is configured such that a code rate of the error correction code is larger than a Shannon capacity for noise exhibited by the QKD data, or that the error correction code, after decoding the QKD data, leaves errors in corrected QKD data with a probability of at least 98%, generating a first output set of data blocks based on the decoding, computing local error detection information on each data block of a second input set of data blocks, and generating a second output set of data blocks based on the local error detection information and based on remote error detection information as suggested by Walenta to also include the error correction step and the error detection step are performed in any order; in response to the error detection step being performed before the error correction step, the second input set of data blocks comprises the set of data blocks of the device and the first input set of data blocks comprises the second output set of data blocks as taught by Aldereguia. One of ordinary skill in the art would have been motivated to do so because incorporating Aldereguia’s error-detection-before-correction approach would have predictably enabled errors to be identified before applying ECC correction, thereby allowing the identified erroneous data to be selectively corrected and improving the reliability of the corrected data.
The references as combined above fails to disclose
in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks.
However, ANDERSON in the same field of endeavor discloses
in response to the error correction step being performed before the error detection step,( ANDERSON, [ln35-36]” Each block 12 thus comprises subblocks, each having 96 (two pairs of 48) data byte positions and three pairs of subblock check bytes C₁, C₂, and C₃. In addition, four check bytes CR₁-CR₄ for data integrity checking after ECC correction”).
the first input set of data blocks comprises the set of data blocks of the device( ANDERSON, [ln35-36]” Fig. 1 illustrates the data format of a disk track that embodies a two-level code structure” and “Each block 12 is divided into fixed length subblocks 14.”).
the second input set of data blocks comprises the first output set of data blocks. ( ANDERSON, [ln30-37, ln25-30]” four check bytes CR₁-CR₄ for data integrity checking after ECC correction and two check bytes C₀ for second level error correction are appended to the end of each block 12 in a block check byte area 15” and “First level error patterns are also used by the second level syndrome generator 29 in calculating second level syndromes, ensuring that the second level syndromes reflect corrected first level data”).
Therefore it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to further include in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks as suggested by ANDERSON. One of ordinary skill in the art would have been motivated to do so because incorporating ANSERSON’s two-level error correction and subsequent data-integrity checking would have predictably enabled corrected data to be checked for remaining errors, thereby improving the reliability and integrity of the resulting data.
As per claim 4, the references as combined above discloses the device According to claim 1. Walenta further discloses wherein the instructions, when executed by the at least one processor, further enable the device to
receive the remote error correction information from the remote device, (Walenta, [Para 2.4 ]” Bob calculates all syndromes for a constant expected error rate, and forwards them to Alice through an authenticated channel.”)
wherein the remote error correction information comprises error correction information computed by the remote device on the corresponding data block of the remote device based on the error correction code. (Walenta, [Para 2.4 ]” Our FPGA implementation for LDPC performs FEC on blocks of 1944 bit length and provides rates up to 235 Mbps at 62.5MHz clock frequency with ten decoding iterations” and “Bob calculates all syndromes for a constant expected error rate, and forwards them to Alice through an authenticated channel”).
As per claim 5, the references as combined above discloses the device according to claim 1. Walenta further discloses wherein the instructions, when executed by the at least one processor, enable the device to generate the first output set of data blocks based on the decoding by:
retaining a decoded data block of the first input set of data blocks in response to the decoding being successful; (Walenta, [Para 2.4 ]” Once we obtain 512 blocks of 1944 error corrected and verified bits…”)
discarding a data block of the first input set of data blocks in response to the decoding failing; (Walenta, [Para 2.4 ]” If an error occurred, the corresponding block is discarded”) and
generating the first output set of data blocks based on the retained data blocks. (Walenta, [Para 2.4 ]” Once we obtain 512 blocks of 1944 error corrected and verified bits, Alice compares them with her original random bit sequence…”).
As per claim 14, ELKOUSS discloses a method applied to a device, the method comprising:
obtaining Quantum Key Distribution (QKD) data,( ELKOUSS, [col.3 ln30-33]” the method comprising quantum key distribution (QKD) for distributing a raw key of length N between at least a first and a second party, the method comprising the second party: - receiving the raw key through a quantum channel;”)
dividing the QKD data into a set of data blocks, ( ELKOUSS, [col.13 ln5-10]” Both Alice and Bob now split the received raw key in strings or words of length n with n smaller than N.”) wherein each data block of the set of data blocks of the device corresponds to a data block of a remote device, ( ELKOUSS, [ln]” the secure key can be shared. Alternatively, as illustrated in figure 1, a third party is connected via a quantum channel with both Alice and to Bob, and other parties if needed. In this way, a raw key of length N is shared or disseminated”).
determining, based on a Bit Error Rate (BER) or a Signal to Noise Ratio (SNR), an error correction code, ( ELKOUSS, [col.2 ln15-20]” the device further obtains an initial error correction codeword; determines, based on a Signal to Noise Ratio (SNR) and/or Bit Error Rate (BER) of the QKD data,”)
performing an error correction step, ( ELKOUSS, [claim 1]” processing the small words using an error correction code based upon the small words of length n;”) comprising:
performing decoding on each data block of a first input set of data blocks( ELKOUSS, [claim 1 and claim 16]” processing the small words including applying a correction code on the small words and the encoded information from the transmissions from the first party;” and “the first party receiving from the second party through the public classical channel a series of transmissions, each transmission comprising encoded information”) based on the error correction code( ELKOUSS, [ln]” Each word is error-corrected…) and based on remote error correction information, ( ELKOUSS, [col.14 ln30-32]” for each block, i.e. for i = 1 to m, do a. Alice sends s(x.sup.1), i.e. the syndrome of block x.sup.1, to Bob through a classical channel. ”).
and performing an error detection step, ( ELKOUSS, [ln5-10]” identifying incorrectly corrected small words using the information from the N/n transmissions from….”) comprising:
ELKOUSS does not disclose
wherein the error correction code is configured such that a code rate of the error correction code is larger than a Shannon capacity for noise exhibited by the QKD data, or that the error correction code, after decoding the QKD data, leaves errors in corrected QKD data with a probability of at least 98%,
generating a first output set of data blocks based on the decoding,
computing local error detection information on each data block of a second input set of data blocks, and
generating a second output set of data blocks based on the local error detection information and based on remote error detection information, wherein
the error correction step and the error detection step are performed in any order, and
in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks, and
in response to the error detection step being performed before the error correction step, the second input set of data blocks comprises the set of data blocks of the device and the first input set of data blocks comprises the second output set of data blocks.
However, Walenta discloses
wherein the error correction code is configured such that a code rate of the error correction code(Walenta, [Para 2.4]” The LDPC code rate, i.e. the fraction of unpublished information, can be set to fEC (Q) 2 {1/2, 2/3, 3/4, 5/6} to adapt to the expected error rates.”) is larger than a Shannon capacity for noise exhibited by the QKD data, or [that the error correction code, after decoding the QKD data, (Walenta, [Para 2.4]” Alice performs syndrome decoding and checks the parity”)leaves errors in corrected QKD data Walenta, [Para 2.4]” However, there is still a certain probability that uncorrected errors remain after error correction, especially for error rates larger than 6% (see figure 3, left).”) with a probability of at least 98%], (Walenta, [Para 2.4]” Figure 3. (left) Measurement results for different code rates showing the probability that the comparison between Alice and Bob’s verification hash tags indicates at least one remaining error per 2048 bit block of error corrected keys.” The Examiner interprets figure 3 (left) as showing a probability of approximately 0.98 or greater that at least one error remains in an error-corrected key block.).
generating a first output set of data blocks based on the decoding, (Walenta, [Para 2.4]” Alice performs syndrome decoding and checks the parity. If an error occurred, the corresponding block is discarded”).
computing local error detection information on each data block of a second input set of data blocks, (Walenta, [Para 2.4]” The checksums are generated using polynomial hashing [3, 4], with a new random 48-bit seed for each checksum…For each block, the hash, as well as the random choice of hash function, is sent to Alice.”) and
generating a second output set of data blocks based on the local error detection information (Walenta, [Para 2.4]” To detect remaining errors, we implement a subsequent verification step, where Bob transmits a 48-bit hash checksum per LDPC code block to Alice”)and based on remote error detection information, (Walenta, [Para 2.4, 2.5]” For each block, the hash, as well as the random choice of hash function, is sent to Alice. If a checksum mismatch occurs, the associated block is discarded” and “Once we obtain 512 blocks of 1944 error corrected and verified bits, Alice compares them with her original random bit sequence”).
Therefore it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify ELKOUSS to include wherein the error correction code is configured such that a code rate of the error correction code is larger than a Shannon capacity for noise exhibited by the QKD data, or that the error correction code, after decoding the QKD data, leaves errors in corrected QKD data with a probability of at least 98%, generating a first output set of data blocks based on the decoding, computing local error detection information on each data block of a second input set of data blocks, and generating a second output set of data blocks based on the local error detection information and based on remote error detection information as suggested by Walenta. One of ordinary skill in the art would have been motivated to do so because incorporating Walenta’s error correction and verification techniques would improve the reliability of the QKD key-generation process by correcting errors in the sifted key and subsequently detecting and discarding blocks containing residual errors, thereby reducing the likelihood that erroneous key material is retained.
The combination of ELKOUSS and Walenta fails to disclose
the error correction step and the error detection step are performed in any order, and
in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks, and
in response to the error detection step being performed before the error correction step, the second input set of data blocks comprises the set of data blocks of the device and the first input set of data blocks comprises the second output set of data blocks.
However, Aldereguia in the same field of endeavor discloses
the error correction step and the error detection step are performed in any order (Aldereguia, [col.5 ln 15-23]” If the word does not include a parity error, the method of FIG. 2 continues by committing (214) the word. The method of FIG. 2 continues by determining (206) whether only one word includes a parity error. If only one word of the block includes a parity error the method of FIG. 2 continues by correcting (210) the one word that includes the parity error through use of the ECC of the block and committing (212) the corrected word.”).
in response to the error detection step being performed before the error correction step, (Aldereguia, [col.5 ln 15-20]” determining (206) whether only one word includes a parity error… correcting (210) the one word that includes the parity error through use of the ECC of the block”) the second input set of data blocks comprises the set of data blocks of the device(Aldereguia, [col.5 ln 35-37]” receiving (202) a block of data; determining (204) whether a word of the block includes a parity error;”) and the first input set of data blocks comprises the second output set of data blocks. (Aldereguia, [col.5 ln 15-21, col.6 ln 10-15, col.6 ln14-20]” If only one word of the block includes a parity error the method of FIG. 2 continues by correcting (210) the one word that includes the parity error through use of the ECC of the block” and “ The receiver identifies a parity error in only the second byte” and then “The receiver may then correct (210) the second byte…”).
Therefore it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify ELKOUSS to include wherein the error correction code is configured such that a code rate of the error correction code is larger than a Shannon capacity for noise exhibited by the QKD data, or that the error correction code, after decoding the QKD data, leaves errors in corrected QKD data with a probability of at least 98%, generating a first output set of data blocks based on the decoding, computing local error detection information on each data block of a second input set of data blocks, and generating a second output set of data blocks based on the local error detection information and based on remote error detection information as suggested by Walenta to also include the error correction step and the error detection step are performed in any order; in response to the error detection step being performed before the error correction step, the second input set of data blocks comprises the set of data blocks of the device and the first input set of data blocks comprises the second output set of data blocks as taught by Aldereguia. One of ordinary skill in the art would have been motivated to do so because incorporating Aldereguia’s error-detection-before-correction approach would have predictably enabled errors to be identified before applying ECC correction, thereby allowing the identified erroneous data to be selectively corrected and improving the reliability of the corrected data.
The references as combined above fails to disclose
in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks.
However, ANDERSON in the same field of endeavor discloses
in response to the error correction step being performed before the error detection step,( ANDERSON, [ln35-36]” Each block 12 thus comprises subblocks, each having 96 (two pairs of 48) data byte positions and three pairs of subblock check bytes C₁, C₂, and C₃. In addition, four check bytes CR₁-CR₄ for data integrity checking after ECC correction”).
the first input set of data blocks comprises the set of data blocks of the device( ANDERSON, [ln35-36]” Fig. 1 illustrates the data format of a disk track that embodies a two-level code structure” and “Each block 12 is divided into fixed length subblocks 14.”).
the second input set of data blocks comprises the first output set of data blocks. ( ANDERSON, [ln30-37, ln25-30]” four check bytes CR₁-CR₄ for data integrity checking after ECC correction and two check bytes C₀ for second level error correction are appended to the end of each block 12 in a block check byte area 15” and “First level error patterns are also used by the second level syndrome generator 29 in calculating second level syndromes, ensuring that the second level syndromes reflect corrected first level data”).
Therefore it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to further include in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks as suggested by ANDERSON. One of ordinary skill in the art would have been motivated to do so because incorporating ANSERSON’s two-level error correction and subsequent data-integrity checking would have predictably enabled corrected data to be checked for remaining errors, thereby improving the reliability and integrity of the resulting data.
As per claim 16, the substance of the claimed invention is identical or substantially similar to that of claim 4. Accordingly, this claim is rejected under the same rationale.
As per claim 17, the substance of the claimed invention is identical or substantially similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
Claims 2, 3 and 15 are rejected under 35 U.S.C. §103 as being unpatentable over ELKOUSS et al.( WO 2023244105 A1)[hereinafter “ELKOUSS”] in view of Walenta et al. (New Journal of Physics 16 (2014) 013047) [hereinafter “Walenta”] and view of Aldereguia et al (US 9094162 B2) [hereinafter “Aldereguia”] and further in view of ANDERSON et al. (EP 0306196 A2) [hereinafter “ANDERSON”] as applied to claim 1 and claim 14 and in view of Varnica et al.( US 8739009 B1) [hereinafter “Varnica”].
As per claim 2, the references as combined above disclose the device according to claim 1. The combination fails to disclose wherein the instructions, when executed by the at least one processor, further enable the device to:
perform the error correction step one or more times; and
perform the error detection step one or more times, wherein the error correction step(s) and
the error detection step(s) are performed in any order, and
the respective input set of data blocks for the error correction steps and the error detection step(s) comprises the output set of data blocks generated by a previous error correction step or error detection step.
However, Varnica in the same field of endeavor discloses
perform the error correction step one or more times;( Varnica, [col.3, ln20-25]” In the error correction phase, data blocks that are determined to be defective after detection in error recovery mode are iteratively decoded to correct the defect.”) and
perform the error detection step one or more times, wherein the error correction step(s) ( Varnica, [col.3 ln15-21]” The detectors may be used together in error recovery mode. For example, the error recovery system may run a second detector if a first detector fails to return a valid codeword error recovery mode”) and
the error detection step(s) are performed in any order, and
the respective input set of data blocks for the error correction steps and the error detection step(s) comprises the output set of data blocks generated by a previous error correction step or error detection step. ( Varnica, [col.10 ln40-45]” The process continues at step 860 where blocks having erased LLRs are iteratively decoded.”).
Therefore it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include in response to the error correction step being performed before the error detection step, the first input set of data blocks comprises the set of data blocks of the device and the second input set of data blocks comprises the first output set of data blocks as suggested by ANDERSON to further include perform the error correction step one or more times; and perform the error detection step one or more times, wherein the error correction step(s) and the error detection step(s) are performed in any order, and the respective input set of data blocks for the error correction steps and the error detection step(s) comprises the output set of data blocks generated by a previous error correction step or error detection step as suggested by Varnica. One of ordinary skill in the art would have been motivated to do so because incorporating Varnica’s iterative error-detection and error-correction processing would have enabled residual defects remaining after an earlier processing step to be detected and subjected to further corrective decoding , thereby improving the reliability of the decoded data.
As per claim 3, the references as combined above disclose the device according to claim 2. Walenta further discloses wherein the instructions, when executed by the at least one processor, further enable the device to:
perform privacy amplification on a final output set of data blocks, (Walenta, [Para 2.4 ]” The universal hash function is randomly chosen, and the collision probability on at least one of 512 subsequent blocks (corresponding to 995 328 bit input length for privacy amplification) is upper-bounded by "VER 6 7.7×10−11.”).
wherein the final output set of data blocks comprises the output set of data blocks generated by a last error correction step or a last error detection step(Walenta, [Para 2.4 ]” To detect remaining errors, we implement a subsequent verification step, where Bob transmits a 48-bit hash checksum per LDPC code block to Alice…If a checksum mismatch occurs, the associated block is discarded”).
after a predefined criterion is reached. (Walenta, [Para 2.5 ]” Once we obtain 512 blocks
of 1944 error corrected and verified bits, Alice compares them with her original random bit
sequence”).
As per claim 15, the substance of the claimed invention is identical or substantially similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
Claims 6, 13 and 18 are rejected under 35 U.S.C. §103 as being unpatentable over ELKOUSS et al.( WO 2023244105 A1)[hereinafter “ELKOUSS”] in view of Walenta et al. (New Journal of Physics 16 (2014) 013047) [hereinafter “Walenta”] and view of Aldereguia et al (US 9094162 B2) [hereinafter “Aldereguia”] and further in view of ANDERSON et al. (EP 0306196 A2) [hereinafter “ANDERSON”] as applied to claim 1 and claim 17 and in view of BAO et al.( WO 2006003522 A1) [hereinafter “BAO”].
As per claim 6, the references as combined above discloses the device according to claim 5. The combination fails to disclose wherein the instructions, when executed by the at least one processor, enable the device to generate the first output set of data blocks based on the retained data blocks by:
merging two or more retained data blocks; and generating the first output set of data blocks based on the merged data blocks.
However, BAO in the same field of endeavor discloses
wherein the instructions, when executed by the at least one processor, enable the device to generate the first output set of data blocks based on the retained data blocks by:
merging two or more retained data blocks;(BAO, [Page 4]” At each step, Alice and Bob concatenate the retained blocks in their original order”) and
generating the first output set of data blocks based on the merged data blocks. (BAO, [Page 4]”… and obtain respective retained strings”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include wherein the instructions, when executed by the at least one processor, enable the device to generate the first output set of data blocks based on the retained data blocks by: merging two or more retained data blocks; and generating the first output set of data blocks based on the merged data blocks as suggested by BAO. One of ordinary skill in the art would have been motivated to do so because incorporating BAO’s technique of concatenating retained blocks to form a retained string, thereby consolidating successfully retained data into a combined output for subsequent processing, which would predictably facilitate continued reconciliation and key-distillation processing.
As per claim 13, the references as combined above disclose the device according to claim 1. The combination fails to disclose wherein a total number of data blocks of the device is the same as a total number of data blocks of the remote device, and a size of each data block of the device is the same as a size of the corresponding data block of the remote device.
However, BAO in the same field of endeavor disclose
wherein a total number of data blocks of the device is the same as a total number of data blocks of the remote device, (BAO, [Page 8]” At step 203, generate P, a probability string of length n, and S an HT-indicator string using the nonces. Alice and Bob do the following separately, (only Alice's steps for XA are shown but Bob performs similar steps for XB” and “At step 204, generate string XA = {XA [l], ... , XA [n]} by P, for example, for each i, generate a random number r[i] and set XA [i] = l if r[i] S P[i] and zero otherwise.” The examiner interprets the disclosure that Alice and Bob each generate respective strings of length n, and subsequently partition their respective strings into sub-blocks of a predetermined fixed length l, as disclosing that the total number of data blocks generated for Alice is the same as the total number of data blocks generated for Bob .) and a size of each data block of the device is the same as a size of the corresponding data block of the remote device. (BAO, [Page 4]” Alice and Bob systematically partition their respective random raw strings, XA and Xn, into sub-blocks of a predetermined fixed length l.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include wherein a total number of data blocks of the device is the same as a total number of data blocks of the remote device, and a size of each data block of the device is the same as a size of the corresponding data block of the remote device as suggested by BAO. One of ordinary skill in the art would have been motivated to do so because incorporating BAO’s systematic partitioning of Alice’s and Bob’s respective strings into corresponding sub-blocks of the same predetermined fixed length would predictably facilitate consistent block-by-block comparison and error detection between the communicating parties.
As per claim 18, the substance of the claimed invention is identical or substantially similar to that of claim 6. Accordingly, this claim is rejected under the same rationale.
Claims 7, 8, 19, 20 are rejected under 35 U.S.C. §103 as being unpatentable over ELKOUSS et al.( WO 2023244105 A1)[hereinafter “ELKOUSS”] in view of Walenta et al. (New Journal of Physics 16 (2014) 013047) [hereinafter “Walenta”] and view of Aldereguia et al (US 9094162 B2) [hereinafter “Aldereguia”] and further in view of ANDERSON et al. (EP 0306196 A2) [hereinafter “ANDERSON”] as applied to claim 1, 14 and in view of Harrison et al.( US 20090113267 A1) [hereinafter “Harrison”].
As per claim 7, the references as combined above discloses the device according to claim 1. The combination fails to disclose wherein the error correction code is specified by a parity-check matrix.
However, Harrison in the same field of endeavor discloses
wherein the error correction code is specified by a parity-check matrix. (Harrison, [0007]” Linear block codes are defined by generator and parity-check matrices.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include wherein the error correction code is specified by a parity-check matrix as suggested by Harrison. One of ordinary skill in the art would have been motivated to do so because incorporating Harrison’s use of a parity-check matrix to define the error-correction code would have provided a known and efficient mechanism for detecting and correcting errors in received data.
As per claim 8, the references as combined above discloses the device according to claim 7. The combination fails to disclose wherein the remote error correction information comprises a syndrome, the syndrome being based on the parity-check matrix.
However, Harrison discloses
wherein the remote error correction information comprises a syndrome, the syndrome being based on the parity-check matrix (Harrison, [0009]” The product of the received word r and the transpose of the parity-check matrix is called the error syndrome of r, ”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include wherein the remote error correction information comprises a syndrome, the syndrome being based on the parity-check matrix as suggested by Harrison. One of ordinary skill in the art would have been motivated to do so because incorporating Harrison’s syndrome generation based on a parity-check matrix would have provided a known technique for identifying errors in received encoded data and facilitating error correction.
As per claim 19, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
As per claim 20, the substance of the claimed invention is identical or substantially similar to that of claim 8. Accordingly, this claim is rejected under the same rationale.
Claims 9, 11 are rejected under 35 U.S.C. §103 as being unpatentable over ELKOUSS et al.( WO 2023244105 A1)[hereinafter “ELKOUSS”] in view of Walenta et al. (New Journal of Physics 16 (2014) 013047) [hereinafter “Walenta”] and view of Aldereguia et al (US 9094162 B2) [hereinafter “Aldereguia”] and further in view of ANDERSON et al. (EP 0306196 A2) [hereinafter “ANDERSON”] as applied to claim 1 and in view of Yuan et al.( US 20170237559 A1) [hereinafter “Yuan”].
As per claim 9, the references as combined above discloses the device according to claim 1. The combination fails to disclose wherein the instructions, when executed by the at least one processor, enable the device to generate the second output set of data blocks based on the local error detection information and based on remote error detection information by: receiving, from the remote device, the remote error detection information, wherein the remote error detection information comprises error detection information computed by the remote device on the corresponding data block of the remote device; retaining a data block of the second input set of data blocks in response to the local error detection information being equal to the remote error detection information, wherein the local error detection information comprises error detection information computed by the device on each data block of the input set of data blocks; discarding the data block in response to the local error detection information being different from the remote error detection information; and generating the second output set of data blocks based on the retained data blocks.
However, Yuan in the same field of endeavor discloses
receiving, from the remote device, the remote error detection information,( Yuan, [0032]” For each key block, the quantum engines of the partner systems exchange the time sequence identifier and a hash of the key block to synchronize with each other”) wherein the remote error detection information comprises error detection information computed by the remote device on the corresponding data block of the remote device; ( Yuan, [0032]” For each key block, the quantum engines of the partner systems exchange the time sequence identifier and a hash of the key block to synchronize with each other”).
retaining a data block of the second input set of data blocks in response to the local error detection information being equal to the remote error detection information, ( Yuan, [0032]” On the other hand, if the hash matches, the quantum engines ensure the same time sequence identifier is associated with the key blocks at each partner system.”) wherein the local error detection information comprises
error detection information computed by the device on each data block ( Yuan, [0041]” To validate, key manager 134 computes a hash of the key block, ”)of the input set of data blocks;
discarding the data block in response to the local error detection information being different from the remote error detection information; ( Yuan, [0040]” If quantum engine 142 detects a hash mismatch, quantum engine 142 determines a mismatch and notifies quantum engine 132”)and
generating the second output set of data blocks based on the retained data blocks. ( Yuan, [0041]” Quantum engines 132 and 142 provide the key block and the time sequence identifier to key managers 134 and 144, respectively. Key managers 134 and 144 store the key block and the time sequence identifier in key pools 136 and 146.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include receiving, from the remote device, the remote error detection information, wherein the remote error detection information comprises error detection information computed by the remote device on the corresponding data block of the remote device; retaining a data block of the second input set of data blocks in response to the local error detection information being equal to the remote error detection information, wherein the local error detection information comprises error detection information computed by the device on each data block of the input set of data blocks; discarding the data block in response to the local error detection information being different from the remote error detection information; and generating the second output set of data blocks based on the retained data blocks as suggested by Yuan. One of ordinary skill in the art would have been motivated to do so because incorporating Yuan’s validation and synchronization technique would enable corresponding key blocks maintained by the respective devices to be compared and selectively retained or discarded based on whether their associated hashes match, thereby ensuring that only consistent, synchronized data blocks are maintained for subsequent use.
As per claim 11, the references as combined above disclose the device according to claim 1. The combination fails to disclose wherein the local error detection information comprises a hash value.
However, Yuan in the same field of endeavor discloses wherein the local error detection information comprises a hash value. (Yuan, [0041]” To validate, key manager 134 computes a hash of the key block,”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include wherein the local error detection information comprises a hash value as suggested by Yuan. One of ordinary skill in the art would have been motivated to do so because incorporating Yuan’s validation and synchronization technique would enable corresponding key blocks maintained by the respective devices to be compared and selectively retained or discarded based on whether their associated hashes match, thereby ensuring that only consistent, synchronized data blocks are maintained for subsequent use.
Claim 10 is rejected under 35 U.S.C. §103 as being unpatentable over ELKOUSS et al.( WO 2023244105 A1)[hereinafter “ELKOUSS”] in view of Walenta et al. (New Journal of Physics 16 (2014) 013047) [hereinafter “Walenta”] and view of Aldereguia et al (US 9094162 B2) [hereinafter “Aldereguia”] and further in view of ANDERSON et al. (EP 0306196 A2) [hereinafter “ANDERSON”] as applied to claim 1 and in view of Yuan et al.( US 20170237559 A1) [hereinafter “Yuan”] as applied to claim 9 and further in view of BAO et al.( WO 2006003522 A1) [hereinafter “BAO”].
As per claim 10, the references as combined above discloses the device according to claim 9. The combination fails to disclose wherein the instructions, when executed by the at least one processor, enable the device to generate the second output set of data blocks based on the retained data blocks by: merging two or more retained data blocks; and generating the second output set of data blocks based on the merged data blocks.
However, BAO in the same field of endeavor disclose when executed by the at least one processor, enable the device to generate the second output set of data blocks based on the retained data blocks by:
merging two or more retained data blocks;(BAO, [Page 4]” At each step, Alice and Bob concatenate the retained blocks in their original order”) and
generating the second output set of data blocks based on the merged data blocks. (BAO, [Page 4]”… and obtain respective retained strings”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include receiving, from the remote device, the remote error detection information, wherein the remote error detection information comprises error detection information computed by the remote device on the corresponding data block of the remote device; retaining a data block of the second input set of data blocks in response to the local error detection information being equal to the remote error detection information, wherein the local error detection information comprises error detection information computed by the device on each data block of the input set of data blocks; discarding the data block in response to the local error detection information being different from the remote error detection information; and generating the second output set of data blocks based on the retained data blocks as suggested by Yuan to further include wherein the instructions, when executed by the at least one processor, enable the device to generate the second output set of data blocks based on the retained data blocks by: merging two or more retained data blocks; and generating the second output set of data blocks based on the merged data blocks as taught by BAO. One of ordinary skill in the art would have been motivated to do so because incorporating BAO’s technique of concatenating retained blocks to form a retained string, thereby consolidating successfully retained data into a combined output for subsequent processing, which would predictably facilitate continued reconciliation and key-distillation processing.
Claim 12 is rejected under 35 U.S.C. §103 as being unpatentable over ELKOUSS et al.( WO 2023244105 A1)[hereinafter “ELKOUSS”] in view of Walenta et al. (New Journal of Physics 16 (2014) 013047) [hereinafter “Walenta”] and view of Aldereguia et al (US 9094162 B2) [hereinafter “Aldereguia”] and further in view of ANDERSON et al. (EP 0306196 A2) [hereinafter “ANDERSON”] as applied to claim 1 and in view of Yuan et al.( US 20170237559 A1) [hereinafter “Yuan”] as applied to claim 11 and further in view of Matsumoto et al.( US 7881472 B2) [hereinafter “Matsumoto”].
As per claim 12, the references as combined above disclose the device according to claim 11. The combination fails to disclose wherein the hash value comprises a check value generated by a cyclic redundancy check (CRC).
However, Matsumoto in the same field of endeavor discloses
wherein the hash value comprises a check value generated by a cyclic redundancy check (CRC)( Matsumoto, [col.3 ln54-65 ]” The quantum key distributing method includes a check matrix generating step at which the respective communication apparatuses generate an identical parity check matrix (a matrix with an element "0" or "1") (corresponding to steps S1 and S11 according to an embodiment described later); a cyclic code generating step at which the communication apparatus on the transmission side generates a cyclic code (CRC: Cyclic Redundancy Check) for error detection (corresponding to step S2);”).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify the system created by combination of ELKOUSS, Walenta ANDERSON and Aldereguia to include wherein the hash value comprises a check value generated by a cyclic redundancy check (CRC) as suggested by Matsumoto. One of ordinary skill in the art would have been motivated to do so because incorporating Matsumoto’s CRC-based error-detection technique would have predictably provided an addition check for detecting residual errors in the key before use, thereby reducing the likelihood that erroneous or mismatched key data would be accepted.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure.
Zhang et al, (US 9363036 B1) discloses “Methods And Apparatus For Defect Detection And Correction Via Nonbinary Iterative Decoding “.
FRITH et al, (WO 2019069103 A1) discloses “a system and method for quantum-safe authentication, encryption and decryption of information”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Komi N. AMEVIGBE whose telephone number is (571)272-3381. The examiner can normally be reached Monday-Friday 2pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Carl Colin can be reached at (571) 272-3862. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.N.A./Examiner, Art Unit 2493
/CARL G COLIN/Supervisory Patent Examiner, Art Unit 2493
