DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: ”component configured to”, “component is further configured to”, in claims 4, 5, 6, 12, 13, 14.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,339,740, hereinafter referred to as “ ’740 ” in view of Hasbun et al., U.S. Patent 2019/0347043, hereinafter referred to as “Hasbun”.
Claim 1 of the instant application maps to claim 1 of ‘740.
Claim 2 of the instant application maps to claim 2 of ‘740.
Claim 3 of the instant application maps to claim 3 of ‘740.
Claim 4 of the instant application maps to claim 4 of ‘740.
Claim 5 of the instant application maps to claim 5 of ‘740.
Claim 6 of the instant application maps to claim 6 of ‘740.
Claim 8 of the instant application maps to claim 7 of ‘740.
Claim 9 of the instant application maps to claim 8 of ‘740.
Claim 10 of the instant application maps to claim 9 of ‘740.
Claim 11 of the instant application maps to claim 10 of ‘740.
Claim 12 of the instant application maps to claim 11 of ‘740.
Claim 13 of the instant application maps to claim 12 of ‘740.
Claim 14 of the instant application maps to claim 13 of ‘740.
Claim 15 of the instant application maps to claim 14 of ‘740.
Claim 16 of the instant application maps to claim 15 of ‘740.
Claim 17 of the instant application maps to claim 16 of ‘740.
Claim 18 of the instant application maps to claim 17 of ‘740.
Claim 19 of the instant application maps to claim 18 of ‘740.
Referring to claim 1, ‘740 discloses all the limitations (See claim 1 of ‘740) except for “a set of data pins” and “a first pin for communicating one or more codewords…wherein the first pin is different than the set of pins”. However, ‘740 discloses channels instead of pins.
Hasbun discloses a memory system (See Hasbun, paragraph 0012). Hasbun discloses a DMI pin or a link error correction code (ECC) pin, that is different than the data pins (See Hasbun, paragraph 0027).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory of ‘740 with the pins including ECC pin that different than data pins of Hasbun. This would have been obvious to do because it is compatible with low power double data rate specification (See Hasbun, paragraph 0027).
Referring to claims 2-6, ‘740 and Hasbun disclose all the limitations (See above rejection of claim 1). ‘740 maps claims 2-6 to instant application claims 2-6.
Referring to claim 7, ‘740 and Hasbun disclose all the limitations (See above rejection of claim 1) and Hasbun discloses the memory can be DRAM (See Hasbun, paragraph 00039).
Referring to claim 8, ‘740 discloses all the limitations (See claim 7 of ‘740) except for “one or more data pins” and “a first pin different than the one or more data pins”. However, ‘740 discloses channels instead of pins.
Hasbun discloses a memory system (See Hasbun, paragraph 0012). Hasbun discloses a DMI pin or a link error correction code (ECC) pin, that is different than the data pins (See Hasbun, paragraph 0027).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory of ‘740 with the pins including ECC pin that different than data pins of Hasbun. This would have been obvious to do because it is compatible with low power double data rate specification (See Hasbun, paragraph 0027).
Referring to claims 9-16, ‘740 and Hasbun disclose all the limitations (See above rejection of claim 8). ‘740 maps claims 8-15 to instant application claims 9-16.
Referring to claim 17, ‘740 discloses all the limitations (See claim 16 of ‘740) except for “a first pin” and “one or more data pins different than the first pin”. However, ‘740 discloses channels instead of pins.
Hasbun discloses a memory system (See Hasbun, paragraph 0012). Hasbun discloses a DMI pin or a link error correction code (ECC) pin, that is different than the data pins (See Hasbun, paragraph 0027).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory of ‘740 with the pins including ECC pin that different than data pins of Hasbun. This would have been obvious to do because it is compatible with low power double data rate specification (See Hasbun, paragraph 0027).
Referring to claims 18-19, ‘740 and Hasbun disclose all the limitations (See above rejection of claim 17). ‘740 maps claims 17-18 to instant application claims 18-19.
Referring to claim 20, ‘740 and Hasbun disclose all the limitations (See above rejection of claim 17) and Hasbun discloses the memory can be DRAM (See Hasbun, paragraph 00039).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-10, 12-14, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Niu et al., U.S. Patent App. Pub. 2018/0046541, hereinafter referred to a “Niu”, in view of Hasbun et al., U.S. Patent 2019/0347043, hereinafter referred to as “Hasbun”.
Referring to claim 1, Niu discloses a memory system (See Niu, paragraph 0032). – A system, comprising:
Niu discloses a host (See Niu, paragraph 0081). – a host device;
Niu discloses the system includes a DRAM with chips for storing data (See Niu, paragraphs 0056 and 0057). – a memory device including an array of memory cells;
Niu discloses the chips having pins to enable connection to computer motherboard to provide data for read and write processes (See Niu, paragraphs 0009 and 0056). – set of data pins for communicating data between the host device and the memory device; and
NIU discloses delivering data via pins (See Niu, paragraphs 0009, 0026, and 0056). NIU discloses ECC bits are generated to correct bit errors of the DRAM (See Niu, paragraph 0062). – a first pin for communicating one or more codewords between the memory device and the host device, and wherein the one or more codewords are for error detection or correction of the data.
Niu does not disclose “wherein the first pin is different than the set of data pins”.
Hasbun discloses a memory system (See Hasbun, paragraph 0012). Hasbun discloses a DMI pin or a link error correction code (ECC) pin, that is different than the data pins (See Hasbun, paragraph 0027).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory of Niu with the pins including ECC pin that different than data pins of Hasbun. This would have been obvious to do because it is compatible with low power double data rate specification (See Hasbun, paragraph 0027).
Referring to claim 2, Niu and Hasbun disclose all the limitations (See rejection of claim 1) including Hasbun discloses a DMI pin (See Hasbun, paragraph 0027). - The system of claim 1, wherein the first pin comprises a DMI pin.
Referring to claim 3, Niu and Hasbun disclose all the limitations (See rejection of claim 1) including Niu discloses bursts for memory transactions (See Niu, paragraph 0026 and 0083). - The system of claim 1, further comprising: a communication component configured to communicate, in a same burst interval, the one or more codewords via the first pin and the data via the set of data pins.
Referring to claim 4, Niu and Hasbun disclose all the limitations (See rejection of claim 1) including Niu discloses an ECC chip that generates ECC bits (See Niu, paragraphs 0015 and 0062). – The system of claim 1, further comprising: an error correction and detection component configured to generate a codeword for error correction based at least in part on the data, the one or more codewords comprising the codeword.
Referring to claim 5, Niu and Hasbun disclose all the limitations (See rejection of claim 1) including Niu discloses an ECC chip that generates ECC bits (See Niu, paragraphs 0015 and 0062). Niu discloses using the ECC for doing a parity check on each of the burst of data, therefore multiple ECC for each burst portion of the memory transaction (See Niu, paragraph 0016). – The system of claim 1, further comprising: an error correction and detection component configured to generate a first codeword and a second codeword for error correction, wherein the first codeword is based at least in part on a first portion of the data and the second codeword is based at least in part on a second portion of the data, the one or more codewords comprising the first codeword and the second codeword.
Referring to claim 7, Niu and Hasbun disclose all the limitations (See rejection of claim 1) including Niu disclose the memory is DRAM (See Niu, paragraph 0015). - The system of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) device.
Referring to claim 8, An apparatus, comprising:
Niu discloses the memory includes a DRAM with chips for storing data (See Niu, paragraphs 0056 and 0057). - an array of memory cells configured to store data; and
Niu discloses a memory controller (See Niu, paragraph 0056). Niu discloses the chips having pins to enable connection to computer motherboard to provide data for read and write processes (See Niu, paragraphs 0009 and 0056). NIU discloses ECC bits are generated to correct bit errors of the DRAM (See Niu, paragraph 0062). - a controller configured to communicate the data via one or more data pins and communicate one or more codewords, wherein the one or more codewords are for error detection or correction of the data.
Niu does not disclose “via a first pin different than the one or more data pins”.
Hasbun discloses a memory system (See Hasbun, paragraph 0012). Hasbun discloses a DMI pin or a link error correction code (ECC) pin, that is different than the data pins (See Hasbun, paragraph 0027).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory of Niu with the pins including ECC pin that different than data pins of Hasbun. This would have been obvious to do because it is compatible with low power double data rate specification (See Hasbun, paragraph 0027).
Referring to claim 9, Niu and Hasbun disclose all the limitations (See rejection of claim 8) including Hasbun discloses a DMI pin (See Hasbun, paragraph 0027). - The apparatus of claim 8, wherein the first pin comprises a DMI pin.
Referring to claim 10, Niu and Hasbun disclose all the limitations (See rejection of claim 8) including Niu discloses bursts for memory transactions (See Niu, paragraph 0026 and 0083). - The apparatus of claim 8, wherein the controller is further configured to communicate the data and the one or more codewords during a same burst interval.
Referring to claim 12, Niu and Hasbun disclose all the limitations (See rejection of claim 8) including Niu discloses an ECC chip that generates ECC bits (See paragraphs 0015 and 0062). - The apparatus of claim 8, further comprising: an error correction code component configured to detect or correct errors based at least in part on receiving the one or more codewords.
Referring to claim 13, Niu and Hasbun disclose all the limitations (See rejection of claim 12) including Niu discloses using the ECC for doing a parity check on each of the burst of data, therefore multiple ECC for each burst portion of the memory transaction (See paragraph 0016). - The apparatus of claim 12, wherein the error correction code component is further configured to: detect or correct one or more errors in a first portion of the data based at least in part on a first codeword of the one or more codewords; and detect and correct one or more errors in a second portion of the data based at least in part on a second codeword of the one or more codewords.
Referring to claim 14, Niu and Hasbun disclose all the limitations (See rejection of claim 12) including Niu detecting one or more errors and correcting the errors in the DRAM (See paragraph 0020). - The apparatus of claim 12, wherein the error correction code component is further configured to: detect or correct one or more errors in at least a portion of the data based at least in part on a first codeword of the one or more codewords; and detect and correct one or more errors in at least the portion of the data, the first codeword, or both based at least in part on a second codeword of the one or more codewords.
Referring to claim 17, Niu discloses a method (See Niu, paragraph 0015). - A method, comprising:
Niu discloses the system includes a DRAM with chips for storing data (See Niu paragraphs 0056 and 0057). IU discloses ECC bits are generated to correct bit errors of the DRAM (See Niu paragraph 0062). - generating, by a first device, one or more codewords for error correction based at least in part on data associated with an array of memory cells of the first device; and
Niu discloses an ECC chip for each memory channel, therefore transmitting different ECC on different channels (See Niu, paragraph 0057). Niu discloses the chips having pins to enable connection to computer motherboard to provide data for read and write processes (See Niu, paragraphs 0009 and 0056). Niu discloses bursts for memory transactions (See Niu, paragraph 0026 and 0083). - transmitting, by the first device and to a second device, the one or more codewords and the data during a same burst interval, wherein the one or more codewords are transmitted via a first pin and the data is transmitted via one or more data pins.
Niu does not disclose “one or more data pins different than the first pin”.
Hasbun discloses a memory system (See Hasbun, paragraph 0012). Hasbun discloses a DMI pin or a link error correction code (ECC) pin, that is different than the data pins (See Hasbun, paragraph 0027).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory of Niu with the pins including ECC pin that different than data pins of Hasbun. This would have been obvious to do because it is compatible with low power double data
Referring to claim 18, Niu and Hasbun disclose all the limitations (See rejection of claim 17) including Hasbun discloses a DMI pin (See Hasbun, paragraph 0027). - The method of claim 17, wherein the first pin comprises a DMI pin.
Referring to claim 19, Niu and Hasbun disclose all the limitations (See rejection of claim 17) including Niu discloses an ECC chip that generates ECC bits (See Niu, paragraphs 0015 and 0062). Niu discloses using the ECC for doing a parity check on each of the burst of data, therefore multiple ECC for each burst portion of the memory transaction (See Niu, paragraph 0016). - The method of claim 17, wherein generating the one or more codewords comprises: generating a first codeword based at least in part on a first portion of the data; and generating a second codeword based at least in part on a second portion of the data.
Referring to claim 20, Niu and Hasbun disclose all the limitations (See rejection of claim 17) including Niu disclose the memory is DRAM (See Niu, paragraph 0015). - The method of claim 17, wherein the first device comprises a dynamic random access memory (DRAM) device.
Claim(s) 11 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Niu and Hasbun as applied to claim 8 above, and further in view of Park et al., U.S. Patent App. Pub. 2015/0347331, hereinafter referred to as “Park”.
Referring to claim 11, Niu and Hasbun disclose all the limitations (See rejection of claim 8) except for The apparatus of claim 8, wherein the controller comprises a de- serializer coupled with the one or more data pins and the first pin.
Park discloses a memory controller with a deserializer and data communication in the memory system is performed (See Park, paragraph 0007).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory apparatus of Niu and Hasbun with the deserializer in memory of Park. This would have been obvious to do because a deserializer is used to transmit data between a memory controller and memory device (See Park, paragraph 0007).
Referring to claim 16, Niu and Hasbun disclose all the limitations (See rejection of claim 8) except for The apparatus of claim 8, further comprising: a transmitting component configured to transmit the data and one or more second codewords to a host device, the transmitting component comprising a serializer coupled with the one or more data pins and the first pin.
Park discloses a memory controller with a serializer and data communication in the memory system is performed (See Park, paragraph 0007).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory apparatus of Niu and Hasbun with the deserializer in memory of Park. This would have been obvious to do because a serializer is used to transmit data between a memory controller and memory device (See Park, paragraph 0007).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Niu and Hasbun as applied to claim 8 above, and further in view of Shibata, U.S. Patent App. Pub. 2009/0006687, hereinafter referred to as “Shibata”.
Referring to claim 15, Niu and Hasbun disclose all the limitations (See rejection of claim 8) except for The apparatus of claim 8, further comprising: a data bus inversion decoder for decoding data bus inversion data; and a data bus inversion encoder for encoding data bus inversion data.
Shibata discloses a memory and encoding and decoding circuit with bit inversion on the bus (See Shibata, paragraphs 0018, 0053, and 0060).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to combine the memory apparatus of Niu and Hasbun with the encoding and decoder for bit inversion on the memory bus of Shibata. This would have been obvious to do because it provides data transferring in RAM (See Shibata, paragraphs 0104-0105).
Allowable Subject Matter
Claims 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the above Double Patenting rejection is also overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent App. Pub. 2023/0185662 to Ayyapureddi
- Memory array with error correction and pins
U.S. Patent App. Pub. 2019/0130950 to Kim et al.
- Memory with DMI pad also used for parity
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D MANOSKEY whose telephone number is (571)272-3648. The examiner can normally be reached M-F 7:30am to 3:30pm.
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/JOSEPH D MANOSKEY/Primary Examiner, Art Unit 2113 July 10, 2026
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