Prosecution Insights
Last updated: October 01, 2026
Application No. 19/244,944

MANAGING DIFFERING ERASE BLOCK SIZES

Non-Final OA §102§112§DOUBLEPATENT
Filed
Jun 20, 2025
Priority
Oct 31, 2017 — continuation of 10/545,687 +3 more
Examiner
KHAN, MASUD K
Art Unit
2139
Tech Center
2100 — Computer Architecture & Software
Assignee
Pure Storage Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
398 granted / 455 resolved
+32.5% vs TC avg
Moderate +7% lift
Without
With
+6.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
18 currently pending
Career history
483
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
63.5%
+23.5% vs TC avg
§102
16.7%
-23.3% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 455 resolved cases

Office Action

§102 §112 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,366,972. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is reciting all limitations of parent patent broader. For better understanding a tabular comparison is presented. Parent patent Instant application A method, comprising: A method, comprising: identifying a change to solid state memory of a storage system; identifying data to be rebuilt responsive to the change to the solid state storage memory; allocating an erase block to receive rebuilt data, wherein the erase block receiving the rebuilt data has a differing size than an erase block containing the data to be rebuilt prior to the change; identifying an erase block to receive rebuilt data, wherein the erase block receiving the rebuilt data and an erase block from which the data is received have differing sizes; and mapping contents of the erase block from which the rebuilt data is received to an offset and a length within the erase block receiving the data, and to an offset within a RAID stripe; and mapping a logical address to the erase block receiving the rebuilt data. writing the rebuilt data into the receiving erase block. Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,366,972. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is reciting all limitations of parent patent broader. For better understanding a tabular comparison is presented. Parent patent Instant application A method, comprising: identifying a change to solid state memory of a storage system; identifying data to be rebuilt responsive to the change to the solid state storage memory; allocating an erase block to receive rebuilt data, wherein the erase block receiving the rebuilt data has a differing size than an erase block containing the data to be rebuilt prior to the change; mapping contents of the erase block from which the rebuilt data is received to an offset and a length within the erase block receiving the data, and to an offset within a RAID stripe; and mapping contents of the erase block from which the data is received to an offset and a length within the erase block receiving the data, and to an offset within a RAID stripe. writing the rebuilt data into the receiving erase block. Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,366,972. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is reciting all limitations of parent patent broader. For better understanding a tabular comparison is presented. Parent patent Instant application wherein there is more than one erase block to receive rebuilt data wherein there is more than one erase block to receive rebuilt data. and wherein at least one erase block of the more than one erase blocks receiving the rebuilt data does not start with metadata. Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,366,972. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is reciting all limitations of parent patent broader. For better understanding a tabular comparison is presented. Parent patent Instant application wherein the erase block receiving rebuilt starts with metadata that maps contents of the erase block to a RAID stripe and a shard within the RAID stripe, and wherein there is more than one erase block to receive rebuilt data. wherein the erase block receiving rebuilt starts with metadata that maps contents of the erase block to a RAID stripe and a shard within the RAID stripe, and wherein there is more than one erase block to receive rebuilt data. Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,366,972. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is reciting all limitations of parent patent broader. For better understanding a tabular comparison is presented. Parent patent Instant application wherein the allocating the erase block to receive rebuilt data is responsive to failure of a solid-state storage drive. wherein the identifying the erase block to receive rebuilt data is responsive to failure of a solid-state storage drive and the erase block receiving the rebuilt data is contained within a replacement solid-state storage drive. Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 12,366,972. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is reciting all limitations of parent patent broader. For better understanding a tabular comparison is presented. Parent patent Instant application mapping a further erase block to receive rebuilt data from a differing RAID stripe than the erase block from which the data is to be received. mapping a further erase block to receive rebuilt data from a differing RAID stripe than the erase block from which the data is to be received. Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,366,972. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is reciting all limitations of parent patent broader. For better understanding a tabular comparison is presented. Parent patent Instant application wherein the differing sizes include the erase block to receive rebuilt data having a larger size than the erase block from which the data is received. wherein the differing sizes include the erase block to receive rebuilt data having a larger size than the erase block from which the data is received. Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 1. Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 2. Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 3. Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 4. Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 6. Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 7. Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 1. Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 2. Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 3. Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 4. Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 6. Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,366,972 under the same rationale of rejection of claim 7. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 19 recites “map more than one erase from which the data is received into the erase block to receive the rebuilt data.” The highlighted section is not clear for a reasonable interpretation as its not particularly stating the unit of “one erase”. For prosecution, examiner is interpreting its as more than one erase block. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Flynn et al. [US 2013/0227236]. Regarding claim 1, Flynn teaches “A method, comprising:” as “The storage device(s) may comprise non-volatile storage devices, such as solid-state storage device(s), that are arranged and/or partitioned into a plurality of addressable, media storage locations.” [¶0073] and “The physical space reservation module 522, in one embodiment, may increase or otherwise change the amount of reserved physical storage capacity. For example, the physical space reservation request module 520 may receive another physical space reservation request, which may or may not be associated with another physical space reservation request.” [¶0195] “identifying an erase block to receive rebuilt data,” as “in a RAID rebuild operation, a second non-volatile storage device may be configured to mirror the contents of a first non-volatile storage device. The data stored on the first logical storage device may be stored sequentially (e.g., in a contextual, log-based format).” [¶0303] “wherein the erase block receiving the rebuilt data and an erase block from which the data is received have differing sizes; and” as “The method may further comprise allocating a logical identifier within a first section of the address space corresponding to a first sector size on the storage device and allocating a logical identifier within a different section of the address space corresponding to a different sector size on the storage device.” [¶0006] “mapping a logical address to the erase block receiving the rebuilt data.” as “The storage layer may leverage the "any-to-any" mappings between LIDs and physical storage resources to manage the logical address space independently of the underlying physical storage devices.” [¶0077] Regarding claim 2, Flynn teaches “wherein the mapping the logical address comprises: mapping contents of the erase block from which the data is received to an offset and a length within the erase block receiving the data, and to an offset within a RAID stripe.” as “a media address refers to an address of a storage resource that uniquely identifies one storage resource from another to a controller that manages a plurality of storage resources, by way of example, a media address includes, but is not limited to: the address of a media storage location, a physical storage unit, a collection of physical storage units (e.g., a logical storage unit), a portion of a media storage unit (e.g., a logical storage unit address and offset, range, and/or extent), or the like.” [¶0075] Regarding claim 3, Flynn teaches “wherein there is more than one erase block to receive rebuilt data.” as “The sequence of writing to logical erase blocks is maintained (e.g., using sequence indicators) so that if the storage metadata 135 is corrupted or lost, the log sequence of storage operations data be replayed to rebuild the storage metadata 135 (e.g., rebuild the "any-to-any" mappings of the storage metadata 135).” [¶0117] Regarding claim 4, Flynn teaches “wherein the erase block receiving rebuilt starts with metadata that maps contents of the erase block to a RAID stripe and a shard within the RAID stripe, and wherein there is more than one erase block to receive rebuilt data.” as “in a RAID rebuild operation, a second non-volatile storage device may be configured to mirror the contents of a first non-volatile storage device. The data stored on the first logical storage device may be stored sequentially (e.g., in a contextual, log-based format).” [¶0303] Regarding claim 5, Flynn teaches “wherein the identifying the erase block to receive rebuilt data is responsive to failure of a solid-state storage drive and the erase block receiving the rebuilt data is contained within a replacement solid-state storage drive.” as “ in the event of a failure, the file system 2916 may be capable of reconstructing the previous state of the file 1.” [¶0428] Regarding claim 6, Flynn teaches “further comprising: mapping a further erase block to receive rebuilt data from a differing RAID stripe than the erase block from which the data is to be received.” as “in a RAID rebuild operation, a second non-volatile storage device may be configured to mirror the contents of a first non-volatile storage device.” [¶0303] Regarding claim 7, Flynn teaches “wherein the differing sizes include the erase block to receive rebuilt data having a larger size than the erase block from which the data is received.” as “the first portion 1952 may comprise a larger proportion of the LID address range and the second portion 1954 (e.g., first portion 1952 comprising 42 bits providing 2 42-1 unique identifiers). Alternatively, where larger storage entitles are used, the ratio between the size of the first and second address portions 1952 and 1954 may be reversed.” [¶0472] Claim 8 recites a computer-readable media with the same set of limitations as claim 1. Therefore, under the rationale of rejection of claim 1, claim 8 is also rejected. Claim 9 recites a computer-readable media with the same subject matter as claim 2. Therefore, under the rationale of rejection of claim 2, claim 9 is also rejected. Claim 10 recites a computer-readable media with the same subject matter as claim 3. Therefore, under the rationale of rejection of claim 3, claim 10 is also rejected. Claim 11 recites a computer-readable media with the same subject matter as claim 4. Therefore, under the rationale of rejection of claim 4, claim 11 is also rejected. Claim 12 recites a computer-readable media with the same subject matter as claim 6. Therefore, under the rationale of rejection of claim 6, claim 12 is also rejected. Claim 13 recites a computer-readable media with the same subject matter as claim 7. Therefore, under the rationale of rejection of claim 7, claim 13 is also rejected. Claim 14 recites a computer-readable media with the same set of limitations as claim 1. Therefore, under the rationale of rejection of claim 1, claim 14 is also rejected. Claim 15 recites a computer-readable media with the same subject matter as claim 2. Therefore, under the rationale of rejection of claim 2, claim 15 is also rejected. Claim 16 recites a computer-readable media with the same subject matter as claim 3. Therefore, under the rationale of rejection of claim 3, claim 16 is also rejected. Claim 17 recites a computer-readable media with the same subject matter as claim 4. Therefore, under the rationale of rejection of claim 4, claim 17 is also rejected. Claim 18 recites a computer-readable media with the same subject matter as claim 6. Therefore, under the rationale of rejection of claim 6, claim 18 is also rejected. Regarding Claim 19, Flynn teaches “map more than one erase from which the data is received into the erase block to receive the rebuilt data.” as “the storage controller reclaims deleted, stale, and/or invalid blocks of the log using a garbage collection system, a groomer, a cleaner agent, or the like. The storage controller, in a further embodiment, uses a forward map to map logical block addresses to media addresses to facilitate use of the append only write structure and garbage collection.” [¶0177] Claim 20 recites a computer-readable media with the same subject matter as claim 7. Therefore, under the rationale of rejection of claim 7, claim 20 is also rejected. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MASUD K KHAN/ Primary Examiner, Art Unit 2132
Read full office action

Prosecution Timeline

Jun 20, 2025
Application Filed
Sep 10, 2026
Non-Final Rejection mailed — §102, §112, §DOUBLEPATENT (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
94%
With Interview (+6.8%)
2y 4m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 455 resolved cases by this examiner. Grant probability derived from career allowance rate.

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